STK15C68-S35I Cypress Semiconductor Corp, STK15C68-S35I Datasheet - Page 4
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STK15C68-S35I
Manufacturer Part Number
STK15C68-S35I
Description
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Datasheet
1.STK15C68-S35I.pdf
(10 pages)
Specifications of STK15C68-S35I
Word Size
8b
Organization
8Kx8
Density
64Kb
Interface Type
Parallel
Access Time (max)
35ns
Operating Supply Voltage (typ)
5V
Package Type
SOIC
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
-40C to 85C
Pin Count
28
Mounting
Surface Mount
Supply Current
75mA
Lead Free Status / Rohs Status
Not Compliant
March 2006
STK15C68
SRAM WRITE CYCLES #1 & #2
Note i:
Note j:
SRAM WRITE CYCLE #1: W Controlled
SRAM WRITE CYCLE #2: E Controlled
NO.
12
13
14
15
16
17
18
19
20
21
ADDRESS
DATA OUT
ADDRESS
DATA OUT
DATA IN
DATA IN
t
WLQZ
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ V
t
t
t
t
t
t
t
t
t
WLWH
DVWH
WHDX
WHAX
WHQX
ELWH
AVWH
AVWL
AVAV
#1
W
W
E
W
E
h, i
SYMBOLS
t
t
t
t
t
t
t
t
WLEH
DVEH
EHDX
EHAX
ELEH
AVEH
AVEL
AVAV
#2
IH
t
AVWL
t
AVEL
18
during address transitions.
18
t
t
t
t
t
t
Alt.
t
t
t
t
WC
WP
CW
DW
WR
OW
DH
AW
WZ
AS
PREVIOUS DATA
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
t
WLQZ
20
t
AVEH
1 7
t
AVWH
17
PARAMETER
t
WLWH
13
t
ELWH
j
14
j
t
AVAV
t
AVAV
12
12
HIGH IMPEDANCE
t
4
ELEH
14
t
WLEH
13
HIGH IMPEDANCE
t
DVWH
15
Document Control # ML0009 rev 0.2
t
DVEH
15
DATA VALID
DATA VALID
STK15C68-25
MIN
25
20
20
10
20
0
0
0
5
MAX
10
STK15C68-35
t
MIN
WHDX
t
35
25
25
12
25
WHAX
0
0
0
5
16
19
t
EHDX
t
EHAX
16
19
(V
t
MAX
WHQX
13
21
CC
STK15C68-45
= 5.0V
MIN
45
30
30
15
30
0
0
0
5
MAX
15
±
10%)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns