DS21348T+ Maxim Integrated Products, DS21348T+ Datasheet - Page 36

• Manufacturer Part Number: DS21348T+
• Description: IC LIU T1/E1/J1 3.3V 44-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21348T+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. STATUS REGISTERS
There are three registers that contain information on the current real-time status of the device, Status
Register (SR) and Receive Information Registers 1 and 2 (RIR1/RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of
the bits in SR, RIR1, and RIR2 are latched bits and some are real time bits. The register descriptions
below list which status bits are latched and which are real time bits. For latched status bits, when an event
or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again. Two of the latched
status bits (RUA1 and RCL) will remain set after reading if the alarm is still present.
The user will always precede a read of any of the three status registers with a write. The byte written to
the register will inform the DS21348 which bits the user wishes to read and have cleared. The user will
write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit
positions. When a one is written to a bit location, that location will be updated with the latest information.
When a zero is written to a bit position, that bit position will not be updated and the previous value will
be held. A write to the status and information registers will be immediately followed by a read of the
same register. The read result should be logically ANDed with the mask byte that was just written and
this value should be written back into the same register to insure that bit does indeed clear. This second
write step is necessary because the alarms and events in the status registers occur asynchronously with
respect to their access via the parallel port. This write-read-write scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the
register. This operation is key in controlling the DS21348 with higher-order software languages.
The bits in the SR register have the unique ability to initiate a hardware interrupt via the INT output pin.
Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the
Interrupt Mask Register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act
differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits will
force the INT pin low whenever they change state (i.e., go active or inactive). The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the
interrupt to occur even if the alarm is still present. The other status bits in SR can force the INT pin low
when they are set. The INT pin will be allowed to return high (if no other interrupts are present) when the
user reads the event bit that caused the interrupt to occur.
Table 5-1. Received Alarm Criteria
ALARM
Note 1:
Note 2:
RUA1
RUA1
RCL
RCL
1
1
Receive carrier loss (RCL) is also known as loss of signal (LOS) or Red Alarm in T1.
See CCR1.5 for details.
E1/T1
E1
T1
E1
T1
Less than 2 zeros in two frames (512 bits)
Over a 3ms window, five or fewer zeros
are received
255 (or 2048)
(G.775)
192 (or 1544)
received
SET CRITERIA
2
2
consecutive zeros received
consecutive zeros are
36 of 76
More than 2 zeros in two frames (512
bits)
Over a 3ms window, six or more zeros
are received
In 255 bit times, at least 32 ones are
received
14 or more ones out of 112 possible
bit positions are received starting with
the first one received
CLEAR CRITERIA