IS43DR16160A-37CBL ISSI, Integrated Silicon Solution Inc, IS43DR16160A-37CBL Datasheet - Page 39

• Manufacturer Part Number: IS43DR16160A-37CBL
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16160A-37CBL

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: WBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 270mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR83200A, IS43/46DR16160A
Extended Mode Register 2 (EMR2)
The Extended Mode Register 2 controls refresh related features. The default value of the EMR(2) is not defined,
therefore the mode register must be programmed during initialization for proper operation. The EMR(2) is written by
asserting LOW on CS, RAS, CAS, WE, HIGH on BA1 and LOW on BA0, while controlling the states of address pins
A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the
EMR(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the
EMR(2). Mode register contents can be changed using the same command and clock cycle requirements during
normal operation as long as all banks are in the precharge state.
EMR(2)
Notes:
1. A3-A6, A8-A12 are reserved for future use and must be set to 0 when programming the EMR(2).
2. Only Industrial and Automotive grade devices support the high temperature Self-Refresh Mode. The controller can set the EMR (2) [A7] bit to
3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
12/16/2010
Address
enable this self-refresh rate if Tc > 85
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued.
A12
A11
A10
Field
BA1
BA0
A3
A9
A8
A6
A7
A5
A4
A2
A1
A0
*1
*1
*1
*1
*1
*1
Register
PASR
Mode
SRF
1
0
0
0
0
0
0
0
0
0
0
*3
o
C while in self-refresh operation. T
A7
A2
0
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
High Temperature Self-Refresh Rate Enable
A0
0
1
0
1
0
1
0
1
oper
Partial Array Self Refresh for 4 Banks
may not be violated.
Enable
Disable
Not defined
Not defined
Full Array
*2
1/2 Array
3/4 array
1/2 array
1/4 Array
1/4 array
00, 01, 10, 11
01, 10, 11
BA[1:0]
10, 11
00, 01
00
11
–
–
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