DS3150T Maxim Integrated Products, DS3150T Datasheet - Page 16
![IC LIU T3/E3/STS-1 48-TQFP](/photos/6/55/65521/48-lqfp_21-0054f_sml.jpg)
DS3150T
Manufacturer Part Number
DS3150T
Description
IC LIU T3/E3/STS-1 48-TQFP
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet
1.DS3150T.pdf
(28 pages)
Specifications of DS3150T
Number Of Drivers/receivers
1/1
Protocol
DS3
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3150T
Manufacturer:
DALLAS
Quantity:
20 000
Company:
Part Number:
DS3150T+
Manufacturer:
Maxim
Quantity:
126
Part Number:
DS3150T+
Manufacturer:
DALLAS
Quantity:
20 000
Company:
Part Number:
DS3150TN+
Manufacturer:
Maxim
Quantity:
852
Company:
Part Number:
DS3150TNC1+
Manufacturer:
AMOTECH
Quantity:
400 000
1.4 Jitter Attenuator
The DS3150 contains an on-board jitter attenuator (JA) that can be placed in the receive path or in the
transmit path or disabled. This selection is made using the RMON and TTS input pins. See
selection details.
Figure 1-8
The jitter attenuator consists of a narrowband PLL to retime the selected clock, a 16 x 2-bit FIFO to
buffer the associated data while the clock is being retimed, and logic to prevent over/underflow of the
FIFO in the presence of very large jitter amplitudes.
The jitter attenuator requires a transmission-quality master clock (i.e., ±20ppm frequency accuracy and
low jitter). When enabled in the receive path, the JA can obtain its master clock from the MCLK pin or
the TCLK pin. If the signal on the MCLK pin is toggling, the JA uses the signal on MCLK as its master
clock. If MCLK is high or floating, the JA uses the signal on the TCLK pin as its master clock. When
enabled in the transmit path, the JA must take its master clock from the MCLK pin. The selected master
clock is also used by the clock and data recovery block.
The JA has a loop bandwidth of master_clock / 2058874 (see corner frequencies in
attenuates jitter at frequencies higher than the loop bandwidth while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
Figure 1-8. Jitter Attenuation and Jitter Transfer
Jitter
Attenuation
(dB)
also shows the jitter transfer of the receiver when the JA is disabled.
-10
-20
-30
0
NOTE: JITTER ATTENUATION AND JITTER TRANSFER ARE NOT TESTED DURING PRODUCTION TEST.
Figure 1-8
25.2Hz (STS-1)
21.7Hz (DS3)
16.7Hz (E3)
10
DS3150
DS3 / E3 / STS-1
Minimum Jitter
Attenuation with
Jitter Attenuator
Enabled
27Hz
shows the minimum jitter attenuation for the device when the JA is enabled.
40Hz
DS3 [GR-253 (1999)]
Category I
100
Frequency (Hz)
1k
1k
16 of 28
DS3 [GR-499 (1995)]
Category I
10k
STS-1
[GR-253 (1999)]
Category II
E3 [TBR24 (1997)]
DS3 [GR-499 (1999)]
Category II
40k 59.6k
100k
>150k
DS3150
Typical
Receiver Jitter
Transfer with
Figure
Jitter Attenuator
Disabled
1M
Table 2-C
1-8). The JA
for