DS2154LN+ Maxim Integrated Products, DS2154LN+ Datasheet - Page 48
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DS2154LN+
Manufacturer Part Number
DS2154LN+
Description
IC TXRX E1 1CHIP 5V ENH 100-LQFP
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS2154L.pdf
(87 pages)
Specifications of DS2154LN+
Number Of Drivers/receivers
1/1
Protocol
E1
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DS2154
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be
inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the DS2154
will load the values present in the Transmit Signaling Register into an outgoing signaling shift register
that is internal to the device. The user can use the Transmit Multiframe bit in Status Register 2 (SR2.5) to
know when to update the signaling bits. The bit will be set every 2ms and the user has 2ms to update the
TSRs before the old data will be retransmitted. ITU specifications recommend that the ABCD signaling
not be set to all 0s because they will emulate a CAS multiframe alignment word.
The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble.
The upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe
synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit
should be set to a 1. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three
remaining bits in TS1 are the spare bits. If they are not used, they should be set to 1. In CCS signaling
mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be
informed when the signaling registers need to be loaded with data. The user has 2ms to load the data
before the old data will be retransmitted.
Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) to
determine, on a channel-by-channel basis, which signaling bits are to be inserted via the TSRs (the
corresponding bit in the TCBRs = 1) and which are to be sourced from the TSER or TSIG pin (the
corresponding bit in the TCBRs = 0). See the Transmit Data Flow diagram
(Figure
14-11) for more
details.
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