DS2181A Maxim Integrated Products, DS2181A Datasheet - Page 17
![IC TXRX CEPT PRIMARY RATE 40-DIP](/photos/6/62/66288/175-40-dip_sml.jpg)
DS2181A
Manufacturer Part Number
DS2181A
Description
IC TXRX CEPT PRIMARY RATE 40-DIP
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS2181A.pdf
(32 pages)
Specifications of DS2181A
Number Of Drivers/receivers
1/1
Protocol
CEPT
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Through Hole
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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RECEIVE SIGNALING Table 7
NOTES: (Applicable only to CAS systems)
1. RSD is valid for the least significant nibble in each indicated timeslot. Timeslot A data appears in bit
2. RSD does not output valid data during timeslots 0 and 16.
RECEIVE MULTIFRAME TIMING Figure 15
RECEIVE TIMING
The receive side output timing set is identical to that found on the transmit side. The user can tie receive
outputs directly to the transmit inputs for drop and insert applications. The received data of RPOS, RNEG
appear at RSER after six RCLK delays, without any change except for the HDB3-to-NRZ conversion
when HDB3 is enabled.
5, B in bit 6, C in bit 7 and D in bit 8.
FRAME #
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
RSD
1
TIMESLOT #
VALID DURING
10, 27
11, 28
12, 29
13, 30
14, 31
15,
-2
1, 18
2, 19
3, 20
4, 21
5, 22
6, 23
7, 24
8, 25
9, 26
, 17
-2
17 of 32
DS2181A