MIC58P42BWM TR Micrel Inc, MIC58P42BWM TR Datasheet - Page 4

• Manufacturer Part Number: MIC58P42BWM TR
• Description: IC DRVR LATCH 8BIT SER IN 18SOIC
• Manufacturer: Micrel Inc
• Type: Driverr

Specifications of MIC58P42BWM TR

• Number Of Drivers/receivers: 8/0
• Voltage - Supply: 5 V ~ 12 V
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Protocol: -
• Other names: MIC58P42BWMTR; MIC58P42BWMTR

MIC58P42
Timing Conditions
(T
A. Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse (Data Hold Time) .............................................................................. 75 ns
C. Minimum Data Pulse Width ..................................................................................................................................... 150 ns
D. Minimum Clock Pulse Width .................................................................................................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ............................................................................................. 300 ns
F. Minimum Strobe Pulse Width ................................................................................................................................... 100 ns
G. Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OUTPUT ENABLE/
RESET pulse resets the output after a current shutdown fault. Thermal limit faults are not latched and require no reset pulse.
MIC58P42 Truth Table
Serial Data
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
Input
A
H
X
L
= +25 C, Logic Levels are V
OUTPUT
ENABLE
STROBE
DATA IN
CLOCK
OUT N
Clock
Input
Shift Register Contents
I
R1
P
1
H
O
L
X
1
A
R2
R
R
P
C
I
O
X
2
1
1
2
B
DD
R
R
R
P
I
O ……
X ……
D
3
2
2
3
3
and V
E
……
……
……
……
……
SS
R
R
R
P
I
O
X
), V
8
8
7
7
8
F
DD
Output
G
Serial
Data
= 5V
R
R
R
P
X
L
7
7
8
8
Strobe
7-52
Input
H
L
R
P
I
X
1
1
1
Latch Contents
R
P
I
X
2
2
2
R
P
I
X
3
3
3
……
……
……
……
R
P
I
X
8
8
8
Output
Enable I
H
L
P
H
1
1
Output Contents
I
P
2
H
2
October 1998
P
I
H …… H
3
3
……P
…… I
Micrel
8
8