CYP15G0101DXB-BBXI Cypress Semiconductor Corp, CYP15G0101DXB-BBXI Datasheet - Page 8

• Manufacturer Part Number: CYP15G0101DXB-BBXI
• Description: IC TXRX HOTLINK 100-LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0101DXB-BBXI

• Package / Case: 100-LBGA
• Protocol: Fibre Channel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.51 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0101DX-EVAL - EVAL BRD FOR HOTLINK II
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Descriptions
CYP(V)(W)15G0101DXB single-channel HOTLink II (continued)
Document Number: 38-02031 Rev. *L
Pin Name
Receive Path Data Signals
RXD[7:0]
RXST[2:0]
RXOP
Receive Path Clock and Clock Control
RXCLK
RXCLKC+
RXRATE
RFEN
Note
7. When REFCLK is configured for half-rate operation (TXRATE
REFCLK.
I/O Characteristics Signal Description
LVTTL output,
synchronous to the
RXCLK output (or
REFCLKinput
when
RXCKSEL = LOW)
LVTTL output,
synchronous to the
RXCLK output (or
REFCLKinput
when
RXCKSEL = LOW)
3-state,
LVTTL output,
synchronous to the
RXCLK output (or
REFCLKinput
when
RXCKSEL = LOW)
3-state,
LVTTL output clock
3-state, LVTTL
output
LVTTL input
static control input,
internal pull-down
LVTTL input,
asynchronous,
internal pull-down
[7]
[7]
[7]
Parallel data output. These outputs change following the rising edge of the selected receive
interface clock.
When the decoder is enabled (DECMODE = HIGH or MID), these outputs represent either
received data or a special character. The status of the received data is represented by the
values of RXST[2:0].
When the decoder is bypassed (DECMODE = LOW), RXD[7:0] become the higher order bits
of the 10-bit received character. See
Parallel status output. These outputs change following the rising edge of the selected
receive interface clock.
When the decoder is bypassed (DECMODE = LOW), RXST[1:0] become the two low-order
bits of the 10-bit received character, while RXST[2] = HIGH indicates the presence of a
comma character in the output register.
When the decoder is enabled (DECMODE = HIGH or MID), RXST[2:0] provide status of the
received signal. See
Receive path odd parity. When parity generation is enabled (PARCTL  LOW), the parity
output is valid for the data on the RXD bus bits.
When parity generation is disabled (PARCTL = LOW), this output driver is disabled (high Z).
Receive character clock output. When configured such that the output data path is clocked
by the recovered clock (RXCKSEL = MID), these true and complement clocks are the receive
interface clocks which are used to control timing of output data (RXD[7:0], RXST[2:0] and
RXOP). This clock is output continuously at either the dual-character rate (1/20
bit-rate) or character rate (1/10
RXRATE.
When configured such that the output data path is clocked by REFCLK instead of recovered
clock (RXCKSEL = LOW), the RXCLK output drivers present a buffered and delayed form
of REFCLK. In this mode, RXCLK and RXCLKC+ are buffered forms of REFCLK that are
slightly different in phase, but follow the frequency and duty cycle of REFCLK. This phase
difference allows the user to select the optimal set-up/hold timing for their specific interface.
Delayed REFCLK+ when RXCKSEL = LOW. Delayed form of REFCLK+, used for transfer
of output data to a host system. This output is only enabled when the receive parallel interface
is configured to present data relative to REFCLK (RXCKSEL = LOW). When RXCKSEL =
LOW, the RXCLKC+ follows the frequency and duty cycle of REFCLK+.
Receive clock rate select. When LOW, the RXCLK recovered clock outputs are
complementary clocks operating at the recovered character rate. Data for the receive channel
should be latched on either the rising edge of RXCLK+ or falling edge of RXCLK–.
When HIGH, the RXCLK recovered clock outputs are complementary clocks operating at
half the character rate. Data for the receive channel should be latched alternately on the rising
edge of RXCLK+ and RXCLK–.
When the output register is operated with REFCLK clocking (RXCKSEL = LOW), RXRATE is
not interpreted and RXCLK± follows the frequency and duty cycle of REFCLK.
Reframe enable. Active HIGH. When HIGH, the Framer in the receive channel is enabled to
frame per the presently enabled framing mode and selected framing character.
=
HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of
Table 16
for a list of receive character status.
th
the serial bit-rate) of the data being received, as selected by
Table 13
for details.
CYW15G0101DXB
CYP15G0101DXB
CYV15G0101DXB
th
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the serial
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