DS90CF383AMTD National Semiconductor, DS90CF383AMTD Datasheet - Page 3

• Manufacturer Part Number: DS90CF383AMTD
• Description: IC TX LVDS FPD 24BIT 56-TSSOP
• Manufacturer: National Semiconductor
• Type: Transmitterr

Specifications of DS90CF383AMTD

• Number Of Drivers/receivers: 4/0
• Protocol: RS644
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Dc: 03+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DS90CF383AMTD

TCIT
TCIP
TCIH
TCIL
LLHT
LHLT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
TJCC
TPLLS
TPDD
Symbol
Symbol
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a
cycle-to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA
chips currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.
TxCLK IN Transition Time (Figure 5 )
TxCLK IN Period (Figure 6 )
TxCLK IN High Time (Figure 6 )
TxCLK IN Low Time (Figure 6)
LVDS Low-to-High Transition Time (Figure 4 )
LVDS High-to-Low Transition Time (Figure 4 )
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN (Figure 6 )
TxIN Hold to TxCLK IN (Figure 6 )
TxCLK IN to TxCLK OUT Delay (Figure 7 ) T
TxCLK IN to TxCLK OUT Delay (Figure 7 )
Transmitter Jitter Cycle-to-Cycle (Figures 12, 13 ) (Note 6)
Transmitter Phase Lock Loop Set (Figure 8 )
Transmitter Power Down Delay (Figure 10 )
Parameter
Parameter
A
=25˚C,V
3
CC
=3.3V
f = 32.5 MHz
f = 32.5 MHz
f = 65 MHz
f = 40 MHz
f = 65 MHz
f = 40 MHz
0.35T
0.35T
−0.30
10.70
12.90
−0.35
10.36
13.93
17.51
21.08
−0.40
12.80
17.20
21.60
26.00
14.7
1.90
4.10
6.30
8.50
3.22
6.79
4.00
8.40
Min
Min
2.5
0
3
3
11.00
13.20
10.71
14.28
17.86
21.43
13.20
17.60
22.00
26.40
0.5T
0.5T
0.75
0.75
2.20
4.40
6.60
8.80
3.57
7.14
4.40
8.80
Typ
Typ
175
240
260
T
0
0
0
0.65T
0.65T
11.20
13.40
11.06
14.63
18.21
21.78
13.60
18.00
22.40
26.80
Max
55.6
Max
0.20
2.40
4.60
6.80
9.00
0.35
3.92
7.49
0.40
4.80
9.20
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225
380
400
100
1.5
1.5
5.5
7.0
10
5
Units
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns