VRS51C1000-40-LG-ISPV2 Ramtron, VRS51C1000-40-LG-ISPV2 Datasheet - Page 8

• Manufacturer Part Number: VRS51C1000-40-LG-ISPV2
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-LG-ISPV2

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details

T
The IAP sub-system handles four different functions.
The IAP function performed is controlled by the
IAPFCT bits as follows:
T
It is important to note that for security reasons, the
IAPSTART bit of the IAPFCTRL register is configured
as read-only by default.
In order to set the IAPSTART bit to 1, the following
operation sequence must be performed first:
The IAPSTART bit can be set to 1.
Once the start bit is set to 1, the IAP sub-system will
read the contents of the IAP Flash Address and Data
registers and hold the VRS51C1000 program counter
at its current value until the IAP operation is
completed. When the IAP operation is complete, the
IAPSTART bit is cleared and the program will continue
executing.
IAP Byte Program Function
The IAP byte program function is used to program a
byte into the specified Flash memory location under
the control of the IAP feature.
program example:
______________________________________________________________________________________________
www.ramtron.com
ABLE
ABLE
Bit
7
6
5
4
3
2
1
0
VRS51C1000
7
10:IAP F
11:IAP F
IAPFCT[1:0] Bits value
Mnemonic
IAPSTART
Unused
Unused
Unused
Unused
Unused
IAPFCT[1:0]
MOV
MOV
MOV
6
LASH
UNCTIONS
C
ONTROL
5
00
01
10
11
IAPFDATA,#55h
IAPFDATA,#AAh
IAPFDATA,#55h
Description
IAP Selected operation Start sequence
-
-
-
-
-
Flash Memory IAP Function
R
EGISTER
IAPFCTRL[15:8]
4
- SFR F7
3
H
Flash Byte Program
Flash Erase Protect
Flash Page Erase
2
See the following
IAP Function
Flash Erase
1
0
IAP_PROG: MOV
IAP Page Erase Function
By using the IAP feature, it is possible to perform a
Page erase of the VRS51C1000 Flash memory (note
that the memory area occupied by the ISP boot
program cannot be page erased). Each page is 512
Bytes in size.
To perform a flash page erase, the page address is
specified by the XY (hex) value written into the
IAPFADHI register (The value 00h must be written into
the IAPFADLO registers)
If the “Y” portion of the IAPFADHI register represents
an even number, the page that will be erased
corresponds to the range XY00h to X(Y+1)FFh
If the “Y” portion of the IAPFADHI register represents
an odd number, the page that will be erased
corresponds to the range X(Y-1)00h to XYFFh
The following program example erases the page
corresponding to the address B000h-CFFFh
;** Erase Flash page located at address B000h to CFFFh.
PageErase: MOV
IAP Chip Erase Function
The IAP chip erase function will erase the entire flash
memory contents with the exception of the ISP boot
program
automatically unprotect the Flash memory.
IAP Chip Protect Function
When the chip protect function is enabled, values read
back from Flash memory will be 00h.
MOV
MOV
MOV
MOV
MOV
MOV
MOV
;**The program Counter will stop until the IAP function is completed
MOV
MOV
MOV
MOV
MOV
MOV
area.
IAPFDATA,#55H
IAPFDATA,#0AAH
IAPFDATA,#55H
SYSCON,#04H
IAPFADHI, FADRSH
IAPFADLO,FADRSL
IAPFDATA,FDATA
IAPFCTRL,#80H
IAPFDATA,#55H
IAPFDATA,#0AAH
IAPFDATA,#55H
SYSCON,#04H
IAPFADHI, #0B0h
IAPFADLO,#00h
IAPFCTRL,#82H
Running
this
;Sequence to Enable Writing
; the IAPSTART bit
;ENABLE IAP FUNCTION
;Set MSB of address to program
;Set LSB of address to program
;Set Data to Program
;Set the IAP Start bit
;Sequence to Enable Writing
; the IAPSTART bit
;ENABLE IAP FUNCTION
;Set MSB of Page address to erase
;Set LSB of address = 00
;SET THE IAP START BIT
page 8 of 48
function
will
also