TMPM332FWUG Toshiba, TMPM332FWUG Datasheet
TMPM332FWUG
Specifications of TMPM332FWUG
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TMPM332FWUG Summary of contents
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... Bit RISC Microcontroller TX03 Series TMPM332FWUG ...
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... TOSHIBA CORPORATION All Rights Reserved ...
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... ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* TMPM332FWUG R ...
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... SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and functions. Register name SAMCR TMPM332FWUG Base Address = 0x0000_0000 Address(Base+) 0x0004 0x000C ...
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... Register name <Bit Symbol> Exmaple: SAMCR<MODE>="000" or SAMCR<MODE[2:0]>="000" <MODE[2:0]> indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width TDATA Function READ WRITE TMPM332FWUG MODE ...
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... TMPM332FWUG ...
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Date Revision 2010/6/11 1 2010/10/6 2 Revision History Comment First Release Contents Revised ...
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...
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... Table of Contents Introduction: Notes on the description of SFR (Special Function Register) under this specification TMPM332FWUG 1.1 Features......................................................................................................................................1 1.2 Block Diagram...........................................................................................................................3 1.3 Pin Layout (Top view)...............................................................................................................4 1.4 Pin names and Functions...........................................................................................................5 1.4.1 Sorted by Pin........................................................................................................................................................................5 1.4.2 Sorted by Port......................................................................................................................................................................9 1.5 Pin Numbers and Power Supply Pins......................................................................................13 2 ...
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... Memory map............................................................................................................................23 4.1.1 Memory Map of TMPM332FWUG..................................................................................................................................24 4.2 SFR area detail.........................................................................................................................25 5. Reset 5.1 Cold reset.................................................................................................................................27 5.2 Warm reset...............................................................................................................................28 5.2.1 Reset period.......................................................................................................................................................................28 5.2.2 After reset..........................................................................................................................................................................28 6. Clock/Mode control 6.1 Features....................................................................................................................................29 6.2 Registers..................................................................................................................................30 6.2.1 Register List.......................................................................................................................................................................30 6.2.2 CGSYSCR (System control register)................................................................................................................................31 6.2.3 CGOSCCR (Oscillation control register) ...
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Executing an ISR 7.1.2.4 Exception exit 7.2 Reset Exceptions......................................................................................................................57 7.3 Non-Maskable Interrupts (NMI)..............................................................................................58 7.4 SysTick....................................................................................................................................58 7.5 Interrupts..................................................................................................................................59 7.5.1 Interrupt Sources................................................................................................................................................................59 7.5.1.1 Interrupt Route 7.5.1.2 Generation 7.5.1.3 Transmission 7.5.1.4 Precautions when using external interrupt pins 7.5.1.5 List of Interrupt Sources ...
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PBDATA (Port B data register) 8.2.2.4 PBCR (Port B output control register) 8.2.2.5 PBFR1 (Port B function register 1) 8.2.2.6 PBPUP (Port B pull-up control register) 8.2.2.7 PBIE (Port B input control register) 8.2.3 Port D (PD0 to PD7)........................................................................................................................................................110 ...
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Type T3............................................................................................................................................................................146 8.3.3 Type T4............................................................................................................................................................................147 8.3.4 Type5 T5..........................................................................................................................................................................148 8.3.5 Type T6............................................................................................................................................................................149 8.3.6 Type T7............................................................................................................................................................................150 8.3.7 Type T8............................................................................................................................................................................151 8.3.8 Type T9............................................................................................................................................................................152 8.3.9 Type T10..........................................................................................................................................................................153 8.3.10 Type T11........................................................................................................................................................................154 8.3.11 Type T12........................................................................................................................................................................155 8.3.12 Type T13........................................................................................................................................................................156 8.3.13 Type T14........................................................................................................................................................................157 8.3.14 Type T15........................................................................................................................................................................158 8.3.15 ...
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Applications using the Capture Function..............................................................................192 9.7.1 One-shot pulse output triggered by an external pulse......................................................................................................192 9.7.2 Frequency measurement..................................................................................................................................................194 9.7.3 Pulse width measurement................................................................................................................................................195 9.7.4 Time Difference Measurement........................................................................................................................................196 10. Serial Channel (SIO/UART) 10.1 Overview.............................................................................................................................197 10.2 Difference in the Specifications of SIO Modules................................................................197 ...
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UART Mode 10.12.3 Transmit Operation......................................................................................................................................................232 10.12.3.1 Operation of Transmission Buffer 10.12.3.2 Transmit FIFO Operation 10.12.3.3 I/O interface Mode/Transmission by SCLK Output 10.12.3.4 Under-run error 10.13 Handshake function...........................................................................................................236 10.14 Interrupt/Error Generation Timing....................................................................................237 10.14.1 RX Interrupts...............................................................................................................................................................237 10.14.1.1 Single Buffer / Double ...
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Generating the Start Condition and a Slave Address.....................................................................................................272 11.6.2.1 Master mode 11.6.2.2 Slave mode 11.6.3 Transferring a Data Word..............................................................................................................................................274 11.6.3.1 Master mode (<MST> = "1") 11.6.3.2 Slave mode (<MST> = "0") 11.6.4 Generating the Stop Condition......................................................................................................................................279 11.6.5 Restart Procedure...........................................................................................................................................................279 ...
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Remote control signal preprocessor (RMC) 13.1 Basic operation....................................................................................................................331 13.1.1 Reception of Remote Control Signal.............................................................................................................................331 13.2 Block Diagram.....................................................................................................................331 13.3 Registers..............................................................................................................................332 13.3.1 Register List...................................................................................................................................................................332 13.3.2 RMCEN (Enable Register)............................................................................................................................................333 13.3.3 RMCREN (Receive Enable Register)............................................................................................................................334 13.3.4 RMCRBUF1(Receive Data Buffer Register 1).............................................................................................................335 13.3.5 RMCRBUF2(Receive ...
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AD Conversion Details..................................................................................................................................................376 14.4.5.1 Starting AD Conversion 14.4.5.2 AD Conversion 14.4.5.3 Top-priority AD conversion during normal AD conversion 14.4.5.4 Stopping Repeat Conversion Mode 14.4.5.5 Reactivating normal AD conversion 14.4.5.6 Conversion completion 14.4.5.7 Interrupt generation timings and AD conversion result ...
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Flash Memory......................................................................................................................407 17.1.1 Features..........................................................................................................................................................................407 17.1.2 Block Diagram of the Flash Memory Section...............................................................................................................409 17.2 Operation Mode...................................................................................................................410 17.2.1 Reset Operation..............................................................................................................................................................411 17.2.2 User Boot Mode (Single chip mode).............................................................................................................................412 17.2.2.1 (1-A) Method 1: Storing a Programming Routine in the Flash Memory 17.2.2.2 (1-B) ...
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AC Electrical Characteristics...............................................................................................471 19.6.1 AC measurement condition...........................................................................................................................................471 19.6.2 Serial Channel (SIO/ UART).........................................................................................................................................471 19.6.2.1 I/O Interface mode 19.6.3 Serial Bus Interface(I2C / SIO).....................................................................................................................................473 19.6.3.1 I2C Mode 19.6.3.2 Clock-Synchronous 8-Bit SIO mode 19.6.4 Event Counter................................................................................................................................................................475 19.6.5 Capture...........................................................................................................................................................................475 19.6.6 External Interrupt...........................................................................................................................................................475 19.6.7 ...
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... TMPM332FWUG The TMPM332FWUG is a 32-bit RISC microprocessor series with an ARM Cortex™-M3 microprocessor core. Product Name TMPM332FWUG Features of the TMPM332FWUG are as follows: 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb® -2 instruction. ・ New 16-bit Thumb instructions for improved program flow ・ ...
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... Clock gear function: The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. 16. Endian Little endian 17. Maximum operating frequency: 40 MHz 18. Operating voltage range 2 3.6 V (with on-chip regulator) 19. Temperature range ・ - degrees (except during Flash writing/ erasing) ・ degrees (during Flash writing/ erasing) 20. Package LQFP64-P-1010-0.50E (10mm × 10mm, 0.5mm pitch) Page 2 TMPM332FWUG ...
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... Block Diagram Cortex-M3 CPU Debug NVIC CG SIO/UART (2ch) I2C/SIO (2ch) CEC RMC Figure 1-1 TMPM332FWUGBlock Diagram I/F FLASH I-Code D-Code I/F RAM System I/F BOOTROM Bus Bridge PORT A,B TMRB (10ch) WDT RTC ADC (8ch) Page 3 TMPM332FWUG ...
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... Pin Layout (Top view) 1.3 Pin Layout (Top view) Figure 1-2 shows the pin layout of TMPM332FWUG. RVDD3 XT1 XT2 NMI MODE RESET INT2/PJ2 INT3/PJ3 TB6OUT/PJ4 RXIN/PE3 TB5IN0/AIN4/PD0 TB5IN1/AIN5/PD1 TB6IN0/AIN6/PD2 TB6IN1/AIN7/PD3 AIN8/PD4 AIN9/PD5 50 TMPM332FWUG 55 Top View 60 64 Figure 1-2 Pin Layout (LQFP64) ...
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... Pin names and Functions Table 1-1 and Table 1-2 sort the input and output pins of the TMPM332FWUG by pin or port. Each table includes alternate pin names and functions for multi-function pins. 1.4.1 Sorted by Pin Table 1-1 Pin Names and Functions Sorted by Pin (1/4) ...
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... I/O port I External interrupt pin I/O port I/O CEC Pin I/O (note) Nch open drain port. I/O I/O port O System clock output O Alarm output I/O I/O port O Timer B output I/O I/O port O Timer B output I/O I/O port O Debug pin Page 6 TMPM332FWUG Function ...
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... With a pull-up and a noise filter (about 30ns (typical value)) I/O port External interrupt pin I/O port External interrupt pin I/O port Timer B output I/O port Inputting signal to remote controller Input port Analog input Inputting the timer B capture trigger Page 7 TMPM332FWUG ...
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... AIN9 Input/ Output I Input port I Analog input I Inputting the timer B capture trigger I Input port I Analog input I Inputting the timer B capture trigger I Input port I Analog input I Inputting the timer B capture trigger I Input port I Analog input I Input port I Analog input Page 8 TMPM332FWUG Function ...
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... Analog input I Input port I Analog input I Input port I Analog input I/O I/O port O Sending serial data I/O I/O port I Receiving serial data I/O I/O port I/O Serial clock input/ output I Handshake input pin I/O I/O port I Inputting signal to remote controller Page 9 TMPM332FWUG ...
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... I/O port TB1IN0 I Inputting the timer B capture trigger PH3 I/O I/O port TB1IN1 I Inputting the timer B capture trigger PI0 I/O I/O port TB0OUT O Timer B output PI1 I/O I/O port TB1OUT O Timer B output PI2 I/O I/O port TB2OUT O Timer B output Page 10 TMPM332FWUG Function ...
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... TEST pin must be left OPEN. AD converter: GND pin (0V) I (note) AVSS must be connected to GND even if the A/D converter is not used. Supplying the AD converter with a reference power supply. I (note) VREFH must be connected to power supply even if A/D converter is not used. Page 11 TMPM332FWUG ...
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... AVDD must be connected to power supply even if A/D converter is not used. DVSS − GND pin DVDD3 − Power supply pin DVDD3 − Power supply pin DVSS − GND pin DVDD3 − Power supply pin DVSS − GND pin RVSS − GND pin RVDD3 − Power supply pin Page 12 TMPM332FWUG Function ...
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... Pin Numbers and Power Supply Pins Table 1-3 Pin Numbers and Power Supplies Power supply Voltage range DVDD3 2.7 to 3.6V AVDD3 RVDD3 Pin No. Pin name PA,PB,PE,PF,PG,PH,PI,PJ,PK,X1,X2,XT1, 9, 39, 44 XT2,RESET,NMI,MODE − Page 13 TMPM332FWUG ...
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... Pin Numbers and Power Supply Pins Page 14 TMPM332FWUG ...
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... Number of Interrupt Inputs The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core. TMPM332FWUG has 37 interrupt inputs. The number of interrupt inputs is reflected in <INTLINESNUM [4:0]> bit of NVIC register. In this product, if read <INTLINESNUM[4:0]> bit, "0y00001" is read out. Product Name ...
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... The Cortex-M3 core has a SysTick timer which can generate SysTick exception. In the TMPM332FWUG, the clock that is input from X1 pin dividing used as a count clock for the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product, when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if this value is read as " ...
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... The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV instruction execution event is input, the core returns from low-power consumption mode caused by WFE in- struction. TMPM332FWUG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 Power Management The Cortex-M3 core provides power management system which uses SLEEPING signals and SLEEPDEEP signals ...
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... Exclusive access Page 18 TMPM332FWUG ...
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... Specification Overview TMPM332FWUG contains the Serial Wire Debug Port (SW-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell™(ETM) unit for instruction trace output.Trace data is output to the dedicated pins (TRACEDATA0, SWV) for the debugging via the on-chip Trace Port Interface Unit (TPIU). ...
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... Serial Wire Data Input/Output Input Serial Wire Clock (Output)(Note) (Serial Wire Viewer Output) TRACE Clock Output TRACE DATA Output0 Value of Related port settings after reset Function Input Output (PxFR) (PxIE) (PxCR Page 20 TMPM332FWUG Pull-up Pull-down (PxPUP) (PxPDN) 1 − − − 0 − 0 − ...
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... Reset Vector Break TMPM332FWUG is prohibited from transmission with debug tools while reset caused by RESET pin is effec- tive.When setting a stop by using reset vector, set the following procedure after reset; set break points from the debug tools, then set the application interrupt and the <SYSRESETREQ> bit of the reset control register to reset again. ...
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... Connection with a Debug Tool Page 22 TMPM332FWUG ...
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... Memory map The memory maps for theTMPM332FWUG are based on the ARM Cortex-M3 processor core memory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. ...
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... Memory map 4.1.1 Memory Map of TMPM332FWUG Figure 4-1 shows the memory map of the TMPM332FWUG. Vencor-Specific CPU Register Region Fault SFR Fault Internal RAM (8K) Fault Internal ROM (128K) Figure 4-1 Memory Map (TMPM332FWUG) Page 24 TMPM332FWUG ...
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... TMRB(10ch) I2C/SIO(2ch) 0x4002_0040 to 0x4002_0057 SIO/UART(2ch) 0x4002_0100 to 0x4002_0133 ADC(8ch) 0x4003_0024 to 0x4003_002F WDT RTC 0x4004_010D CG 0x4004_0230 to 0x4004_023F CEC 0x4004_0428 0x4004_0433 RMC(1ch) to 0x4004 _ 0440 0x4004_ 0473 0x4004_0504 to 0x4004_0507 FLASH 0x4004_0524 to 0x4004_052B 0x4004_0540 to 0x4004_0547 Reserved 0x4004_0550 to 0x4004_0553 0x4004_0560 to 0x4004_0593 Reserved 0x4004_0700 to 0x4004_0707 Page 25 TMPM332FWUG ...
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... SFR area detail Page 26 TMPM332FWUG ...
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... Reset The TMPM332FWUG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from <SYSRESETREQ>, refer to "Cortex-M3 Technical Reference Manual". ...
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... Reset period As a precondition, ensure that the power supply voltage is within the operating range and the internal high- frequency oscillator is providing stable oscillation. To reset the TMPM332FWUG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. 5.2.2 After reset A warm reset initializes the majority of the Cortex-M3 processor core's system control registers and internal function registers ...
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... Controls the system clock ・ Controls the prescaler clock ・ Controls the PLL multiplication circuit ・ Controls the warm-up timer In addition to NORMAL mode, the TMPM332FWUG can operate in three types of low power mode to reduce power consumption according to its usage conditions. Page 29 TMPM332FWUG ...
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... The following table shows the CG-related registers and addresses. System control register Oscillation control register Standby control register PLL selection register System clock selection register Register name CGSYSCR CGOSCCR CGSTBYCR CGPLLSEL CGCKSEL Page 30 TMPM332FWUG Base Address = 0x4004_0200 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 ...
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... Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as 0. 2-0 GEAR[2:0] R/W High-speed clock gear (fc) gear 000: fc 001: Reserved 010: Reserved 011: Reserved 100: fc/2 101: fc/4 110: fc/8 111: Reserved FPSEL - Function Page 31 TMPM332FWUG SCOSEL PRCK GEAR ...
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... Stop 1: Oscillation Specifies operation of the PLL. It stops after reset.Setting the bit is required. Status of Warm-up timer (WUP) 0:Warm-up completed 1: Warm-up operation Enables to monitor the status of the warm-up timer. Operation of warm-up timer 0: don't care 1: starting warm-up Enables to start the warm-up timer. Page 32 TMPM332FWUG ...
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... High-speed oscillator operation after releasing the STOP mode. 0: Stop 1:Oscillation 7-3 − R Read as 0. 2-0 STBY[2:0] R/W Low power consumption mode 000: Reserved 001: STOP 010: SLEEP 011: IDLE 100: Reserved 101: Reserved 110: Reserved 111: Reserved Function Page 33 TMPM332FWUG DRVE RXTEN RXEN STBY ...
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... After reset 0 Bit Bit Symbol Type 31-1 − PLLSEL R Read as 0. Use of PLL 0: Disuse. X1 selected 1: Use Specifies use or disuse of the clock multiplied by the PLL. "X1" is automatically set after reset. Resetting is required when using the PLL. Page 34 TMPM332FWUG PLLSEL Function ...
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... SYSCKFLG R System clock status 0: High-speed (fc) 1: Low-speed (fs) Shows the status of the system clock. Switching the oscillator with <SYSCK> generates time lag to complete. If the output of the oscillator specified in <SYSCK> is read out by <SYSCLKFLG>, the switching has been completed Function Page 35 TMPM332FWUG SYSCK SYSCKFLG ...
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... Clock quadrupled by PLL : Clock specified by CGPLLSEL<PLLSEL> (high-speed clock) : Clock specified by CGSYSCR<GEAR[2:0]> : Clock specified by CGCKSEL<SYSCK> (system clock) : Clock specified by CGSYSCR<FPSEL> : Clock specified by CGSYSCR<PRCK[2:0]> (prescaler clock) : fc, fc/2, fc/4, fc/8 : fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 : fsys : fosc/32 : oscillating : oscillating : stop : fc (no frequency dividing) Page 36 TMPM332FWUG ...
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... PLL <GEAR[2:0]> fpll = fosc 4 T0 CGSYSCR 1/16 1/32 <PRCK[2:0]> 1/2 CGSYSCR <SCOSEL[1:0]> Page 37 TMPM332FWUG ADC conversion clock <ADCLK> CGSYSCR<FPSEL> fperiph (TO peripheal I/O) fgear fsys CGCKSEL <SYSCK> fs Systick Timer input CPU(STCLK) PeripheralI/O prescaler input TMRB, SIO 【AHB-Bus I/O】 CPU(HCLK/FCLK), ROM, RAM, BOOT ROM 【 ...
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... Page 38 TMPM332FWUG Low-speed clock (fs) CGOSCCR<WUPSEL> = "1" − With WUP 1.953 (ms) 3.906 (ms) 7.813 (ms) /input frequency 1.0 (s) /input frequency 2.0 (s) /input frequency 4.0 (s) /input frequency 8.0 (s) ...
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... Switch the system clock to high speed (fgear) CGCKSEL<SYSCKFLG> Read : Confirm that the current state is "0" (the current system clock is fgear) CGOSCCR<XTEN> = "0" : Disable the low-speed oscillation (fs) Note:When switching the system clock, ensure that the switching has been completed by reading the CGSYSCR<SYSCKFLG>. Page 39 TMPM332FWUG ...
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... Clock control 6.3.6 System Clock The TMPM332FWUG offers two selectable system clocks: low-speed or high-speed. The high-speed clock is dividable. Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR[2:0]> register. The actual switching takes place after a slight delay. Note 2: The CEC function uses the low-speed clock as a sampling clock. The allowable margin of error when the CEC function is used is approximately ± ...
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... Note:The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaranteed. Low power consumption mode SLOW IDLE Output the fs clock Output the fsys/2 clock Output the fsys clock Fixed to "0" or "1". clock Page 41 TMPM332FWUG SLEEP STOP ...
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... When the low-speed clock is not used, the SLOW and SLEEP modes cannot be used. Figure 6-2 shows a mode transition diagram. For a detail of sleep-on-exit, refer to "Cortex-M3 Technical Reference Manual." IDLE SLEEP mode NORMAL mode / sleep on exit / sleep on exit SLOW mode / sleep on exit Figure 6-2 Mode Transition Diagram Page 42 TMPM332FWUG / sleep on exit STOP / sleep on exit ...
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... Note 1: Be sure to stop peripheral functions except for the CPU, RTC, I/O ports, CEC and RMC before switch- ing to the SLOW mode. Note 2: In the slow mode, be sure not to perform reset using the Application Interrupt and Reset Control Register <SYSRESETREQ> of the Cortex-M3 NVIC register. Page 43 TMPM332FWUG ...
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... By releasing the SLEEP mode, the device returns to the preceding mode of the SLEEP mode and starts oper- ation. Note:When PA1 (pin number 38) is configured as a debug function pin, it prevents the low power con- sumption mode from being fully effective. Configure PA1 to function as a general-purpose port if the debug function is not used. Page 44 TMPM332FWUG ...
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... Enabled when data is valid. Output Disabled when data is invalid. Input ο Output × Input × Output × CGSTBYCR Mode <STBY[2:0]> STOP 001 SLEEP 010 IDLE 011 Page 45 TMPM332FWUG <DRVE> × "High" level output. ο Depends on (PxIE[m]) ο Depends on (PxCR[m]) Depends on (PxIE[m]) Depends on (PxCR[m]) ...
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... Page 46 TMPM332FWUG SLEEP STOP × × ο * (Note 3) × × × × × × × × × × ο × ο × ...
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... IDLE SLEEP ο ο ο ο ο × ο × ο × ο × ο ο ο ο ο × ο × ο ο ο ο Page 47 TMPM332FWUG STOP ο × × × × × × × × × ο ο ...
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... Not required IDLE → NORMAL Not required SLEEP → NORMAL Auto-warm-up SLEEP → SLOW Not required SLOW → NORMAL (Note 2) SLOW → SLEEP Not required SLOW → STOP Not required STOP → NORMAL Auto-warm-up (Note 3) STOP → SLOW Auto-warm-up Page 48 TMPM332FWUG ...
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... System clock stops Release event occurs. STOP High-speed clock starts oscillating. Warm-up completes. Warm-up starts. System clock starts Release event occurs. SLEEP Oscillation continues. High-speed clock starts oscillating. Warm-up completes. Warm-up starts. System clock starts. Page 49 TMPM332FWUG NORMAL NORMAL ...
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... WFI insutruction/ Release eventoccurs. sleep on exit STOP System clock stops Low-speed clock starts oscillating. Warm-up starts. WFI instruction / sleep on exit SLEEP System clock stops. Page 50 TMPM332FWUG SLOW Warm-up completes. System clock starts. Release event occurs. SLOW System clock starts. ...
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... For detailed descriptions on each exception, refer to "Cortex-M3 Technical Reference Manual". ・ Reset ・ Non-Maskable Interrupt (NMI) ・ Hard Fault ・ Memory Management ・ Bus Fault ・ Usage Fault ・ SVCall (Supervisor Call) ・ Debug Monitor ・ PendSV ・ SysTick ・ External Interrupt Page 51 TMPM332FWUG ...
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... The CG/CPU detects the exception request. The CPU handles the exception request. The CPU branches to the corresponding interrupt service routine (ISR). Necessary processing is executed. The CPU branches to another ISR or returns to the previous program. Page 52 TMPM332FWUG Indicates software handling. See Section 7.1.2.1 Section 7.1.2.2 Section 7.1.2.3 ...
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... Access violation to the Hard Fault region of the memory map Undefined instruction execution or other faults related to instruction ex- ecution System service call with SVC instruction Debug monitor when the CPU is not faulting Pendable system service request Notification from system timer External interrupt pin or peripheral function (Note 2) Page 53 TMPM332FWUG ...
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... Pre-emption Subpriority field field [7:1] [0] [7:2] [1:0] [7:3] [2:0] [7:4] [3:0] [7:5] [4:0] [7:6] [5:0] [7] [6:0] None [7:0] the case of 3-bit configuration, the priority is set as <PRI_n[7:5]> and <PRI_n[4:0]> is "00000". Page 54 TMPM332FWUG Number of Number of pre-emption subpriorities priorities 128 128 1 256 ...
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... Initial value of the main stack Required ISR address Required ISR address Required ISR address Required ISR address Optional ISR address Optional ISR address Optional ISR address Optional ISR address Optional ISR address Optional ISR address Optional ISR address Optional Page 55 TMPM332FWUG ...
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... Pops the eight registers (PC, xPSR r3, r12 and LR) from the stack and adjust the SP. Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. If returning to an exception (Handler Mode SP_main. If returning to Thread Mode, SP can be SP_main or SP_process. Page 56 TMPM332FWUG ...
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... The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT. ・ Reset exception by SYSRESETREQ A reset can be generated by setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control Register. Note:Do not reset with <SYSRESETREQ> in SLOW mode. Page 57 TMPM332FWUG ...
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... SysTick Calibration Value Register also varies with each product. Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms timing when the clock input from MHz. Page 58 TMPM332FWUG ...
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... If interrupts from the external interrupt pins are not used to release standby, they are directly input to the CPU, not through the logic for standby release (route 6). Peripheral function External Port interrupt pin Peripheral function Interruptrequest <INTxEN> Exiting standby mode Clock generator Figure 7-1 Interrupt Route Page 59 TMPM332FWUG CPU ...
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... Set the port control register so that the external pin can perform as an interrupt function pin. Set the peripheral function to make it possible to output interrupt requests. See the chapter of each peripheral function for details. An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pending Page 60 TMPM332FWUG ...
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... TMRB input capture 51 32 INTCAP60 16-bit TMRB input capture 60 33 INTCAP61 16-bit TMRB input capture 61 34 Reserved - 35 Reserved - 36 Reserved - 37 Reserved - 38 Reserved - 39 Reserved - active level (Clearing standby) Selectable Rising edge Falling edge Page 61 TMPM332FWUG CG interrupt mode control register CGIMCGA CGIMCGB CGIMCGB CGIMCGD CGIMCGB CGIMCGC ...
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... Interrupt Source 16-bit TMRB match detection 7 16-bit TMRB match detection 8 16-bit TMRB match detection A/D conversion completion Page 62 TMPM332FWUG active level CG interrupt mode (Clearing standby) control register ...
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... The CPU handles the interrupt. CPU handles interrupt The CPU pushes register contents to the stack before entering the ISR. indicates hardware handling. Details Page 63 TMPM332FWUG indicates software See "7.5.2.2 Preparation" "7.5.2.3 Detection by Clock Generator" "7.5.2.4 Detection by CPU" ...
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... You can assign a priority level by writing to <PRI_n> field in an Interrupt Priority Register of the NVIC register. Details Program for the ISR. Clear the interrupt source if needed. Configure to return to the preceding program of the ISR. ← "1" (interrupt disabled) Page 64 TMPM332FWUG See "7.5.2.6 Interrupt Service Routine (ISR)" ...
Page 85
... Note:m: corresponding bit (6) Configuring the clock generator For an interrupt source to be used for exiting a standby mode, you need to set the active level and enable interrupts in the CGIMCG register of the clock generator. The CGIMCG register is capable of configuring each source. Page 65 TMPM332FWUG ...
Page 86
... Be sure to clear each interrupt request in the ISR. ← active level ← Value corresponding to the interrupt to be used ← "1" (interrupt enabled) ← "1" ← "1" ← "0" Page 66 TMPM332FWUG ...
Page 87
... Therefore, the interrupt source must be cleared. Clearing the interrupt source automatically clears the interrupt request signal from the clock generator interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value in the CGICRCG register. When an active edge occurs again, a new interrupt request will be detected. Page 67 TMPM332FWUG ...
Page 88
... Reserved Reserved Reserved Note:Access to the "Reserved" areas is prohibited. Register name Register name CGICRCG CGNMIFLG CGRSTFLG CGIMCGA CGIMCGB CGIMCGC CGIMCGD - - - - Page 68 TMPM332FWUG Base Address = 0xE000_E000 Address 0x0010 0x0014 0x0018 0x001C 0x0100 0x0104 0x0180 0x0184 0x0200 0x0204 0x0280 0x0284 0x0400 ~ 0x0430 0x0D08 0x0D0C ...
Page 89
... Clears on read of any part of the SysTick Control and Status Register. 15-3 − R Read CLKSOURCE R/W 0: External reference clock 1: CPU clock 1 TICKINT R not pend SysTick 1: Pend SysTick 0 ENABLE R/W 0: Disable 1: Enable If "1" is set, it reloads with the value of the Reload Value Register and starts operation CLKSOURCE Function Page 69 TMPM332FWUG COUNTFLAG TICKINT ENABLE ...
Page 90
... Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32 RELOAD Undefined RELOAD Undefined RELOAD Undefined Read as 0. Reload value Set the value to load into the SysTick Current Value Register when the timer reaches "0". Page 70 TMPM332FWUG Function ...
Page 91
... Read as 0. 23-0 CURRENT R/W [Read] Current SysTick timer value [Write] Clear Writing to this register with any value clears Clearing this register also clears the <COUNTFLAG> bit of the SysTick Control and Status Register CURRENT Undefined CURRENT Undefined CURRENT Undefined Function Page 71 TMPM332FWUG ...
Page 92
... X1 pin by 32.The SysTick Calibration Value Register is set to a value that provides 10 ms timing when the cock input from MHz SKEW - - TENMS TENMS TENMS Reference clock provided 1: No reference clock 0: Calibration value is 10 ms. 1: Calibration value is not 10 ms. Read as 0. Calibration value Reload value to use for 10 ms timing (0x9C4). (Note) Page 72 TMPM332FWUG Function ...
Page 93
... SETENA SETENA SETENA (Interrupt 20) (Interrupt 19) (Interrupt 18 SETENA SETENA SETENA (Interrupt 12) (Interrupt 11) (Interrupt 10 SETENA SETENA - (Interrupt 4) (Interrupt 3) (Interrupt Function Page 73 TMPM332FWUG SETENA SETENA SETENA (Interrupt 25) (Interrupt 24 SETENA SETENA SETENA (Interrupt 17) (Interrupt 16 SETENA SETENA SETENA (Interrupt 9) (Interrupt SETENA SETENA SETENA (Interrupt 1) (Interrupt 0) ...
Page 94
... Interrupt number [33:32] [Write] 1: Enable [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 74 TMPM332FWUG ...
Page 95
... CLRENA CLRENA CLRENA (Interrupt 20) (Interrupt 19) (Interrupt 18 CLRENA CLRENA CLRENA (Interrupt 12) (Interrupt 11) (Interrupt 10 CLRENA CLRENA - (Interrupt 4) (Interrupt 3) (Interrupt Function Page 75 TMPM332FWUG CLRENA CLRENA CLRENA (Interrupt 25) (Interrupt 24 CLRENA CLRENA CLRENA (Interrupt 17) (Interrupt 16 CLRENA CLRENA CLRENA (Interrupt 9) (Interrupt CLRENA CLRENA CLRENA (Interrupt 1) (Interrupt 0) ...
Page 96
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 76 TMPM332FWUG ...
Page 97
... Undefined Undefined Undefined SETPEND SETPEND (Interrupt 12) (Interrupt 11) (Interrupt 10) Undefined Undefined Undefined SETPEND SETPEND - (Interrupt 4) (Interrupt 3) (Interrupt 2) Undefined Undefined Undefined Function Page 77 TMPM332FWUG SETPEND SETPEND SETPEND (Interrupt 25) (Interrupt 24) Undefined Undefined Undefined SETPEND SETPEND SETPEND (Interrupt 17) (Interrupt 16) Undefined Undefined Undefined SETPEND SETPEND SETPEND ...
Page 98
... After reset 0 15 bit symbol - After reset Undefined 7 bit symbol - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Page 78 TMPM332FWUG SETPEND - - (Interrupt 49 Undefined SETPEND SETPEND - (Interrupt 42) (Interrupt 41) Undefined Undefined Undefined SETPEND - - (Interrupt 33) Undefined Undefined Undefined Undefined 8 SETPEND (Interrupt 40) Undefined ...
Page 99
... Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Clear and Interrupt Set-Pending Register bit by writing "1" to the corresponding bit in the Interrupt Clear-Pending Register. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Function Page 79 TMPM332FWUG ...
Page 100
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Page 80 TMPM332FWUG CLRPEND ...
Page 101
... Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" CLRPEND - - - (Interrupt 42) Undefined Undefined Undefined Undefined Undefined Undefined Function Page 81 TMPM332FWUG CLRPEND - - (Interrupt 49) 0 Undefined Undefined CLRPEND CLRPEND (Interrupt 41) (Interrupt 40) Undefined Undefined Undefined CLRPEND CLRPEND - (Interrupt 33) (Interrupt 32) Undefined Undefined Undefined ...
Page 102
... PRI_0 - Priority of interrupt number 3 Read as 0. Priority of interrupt number 2 Read as 0. Priority of interrupt number 1 Read as 0. Priority of interrupt number 0 Read as 0. Page 82 TMPM332FWUG PRI_1 PRI_0 − PRI_4 PRI_9 PRI_8 PRI_13 PRI_12 PRI_17 PRI_16 PRI_21 PRI_20 PRI_25 PRI_24 PRI_29 PRI_28 PRI_33 PRI_32 − ...
Page 103
... The offset must be aligned based on the number of exceptions in the table.This means that the minimum alignment is 32 words that you can use for interrupts.For more interrupts, you must adjust the alignment by rounding up to the next power of two. 6-0 − R Read TBLBASE TBLOFF TBLOFF Function Page 83 TMPM332FWUG TBLOFF ...
Page 104
... This bit self-clears the responsibility of the application to reinitialize the stack. System Reset bit 1: reset system 0: do not reset system Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this bit is also zero cleared. Page 84 TMPM332FWUG ...
Page 105
... Read as 0. 15-13 PRI_5 R/W Priority of Bus Fault 12-8 − R Read as 0. 7-5 PRI_4 R/W Priority of Memory Management 4-0 − R Read PRI_6 PRI_5 (Usage Fault) (Bus Fault) PRI_10 PRI_9 PRI_14 PRI_13 (PendSV Function Page 85 TMPM332FWUG PRI_4 (Memory Management) PRI_8 PRI_12 (Debug Monitor ...
Page 106
... Pended Bus Fault 0: Not pended 1: Pended Memory Management 0: Not pended 1: Pended Usage Fault 0: Not pended 1: Pended SysTick 0: Inactive 1: Active PendSV 0: Inactive 1: Active Read as 0. Debug Monitor 0: Inactive 1: Active SVCall 0: Inactive 1: Active Read as 0. Page 86 TMPM332FWUG USGFAULT BUSFAULT - ENA ENA SYSTICKACT PENDSVACT ...
Page 107
... Active 2 − R Read BUSFAULT R/W Bus Fault ACT 0: Inactive 1: Active 0 MEMFAULT R/W Memory Management ACT 0: Inactive 1: Active Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does not repair stack contents. Function Page 87 TMPM332FWUG ...
Page 108
... Falling edge 011: Rising edge 100: Both edges active level of INT2 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges Reads as undefined. INT2 clear input 0:Disable 1: Enable Read as 0. Page 88 TMPM332FWUG EMST3 - INT3EN 0 0 Undefined EMST2 - ...
Page 109
... If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Function Page 89 TMPM332FWUG ...
Page 110
... Write any value. Read as 0. Reads as undefined. Write "0". Read as 0. active level setting of INT4 standby clear request (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges Page 90 TMPM332FWUG EMST7 - INT7EN 0 0 Undefined 19 18 ...
Page 111
... If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Function Page 91 TMPM332FWUG ...
Page 112
... Write "0". Read as 0. active level setting of INTRTC standby clear request. Set it as shown below. 010: Falling edge active level of INTRTC standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edges Reads as undefined. INTRTC clear input 0:Disable 1: Enable Page 92 TMPM332FWUG Undefined ...
Page 113
... If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited EMCGC EMSTC Function Page 93 TMPM332FWUG INTCEN 0 Undefined 0 ...
Page 114
... Read as 0. Clear interrupt requests. 0_0000: INT0 0_0001: INT1 0_0010: INT2 0_0011: INT3 0_0100: INT4 0_0101: Reserved 0_0110: INTCECRX 0_0111: INTRMCRX 0_1000: INTRTC 0_1001: Reserved 0_1010: Reserved 0_1011: Reserved 0_1100: INTCECTX 0_1101 to 1_1111: setting prohibited. Read as 0. Page 94 TMPM332FWUG ICRCG ...
Page 115
... Bit Symbol Type 31-2 − R Read NMIFLG1 R NMI source generation flag 0: not applicable 1: generated from NMI pin 0 NMIFLG0 R NMI source generation flag 0: not applicable 1: generated from WDT Note:<NMIFLG> are cleared to "0" when they are read Function Page 95 TMPM332FWUG NMIFLG1 NMIFLG0 ...
Page 116
... Debug reset flag(Note1) 0: "0" is written 1: Reset from SYSRESETREQ Write as 0. WDT reset flag 0: "0" is written 1: Reset from WDT RESET pin flag 0: "0" is written 1: Reset from RESET pin Power-on flag 0: "0" is written 1: "1" is set to this bit in initial reset state right after power-on. Page 96 TMPM332FWUG ...
Page 117
... Port Functions 8.1.1 Function Lists TMPM332FWUG has 44 ports. Besides the ports function, these ports can be used as I/O pins for peripheral functions. Table 8-1 and Table 8-2 show the port function table. Table 8-1 Port Function List (Port A to Port B and PortD to PortG) ...
Page 118
... I/O Pull-up ο ο I/O Pull-up − − I/O − ο − I/O Pull-up − − Page 98 TMPM332FWUG Program- mable Function pin Open-drain − TB0IN0, BOOT − TB0IN1 − TB1IN0 − TB1IN1 − TB0OUT − TB1OUT − TB2OUT − ...
Page 119
... When PxOD is set "1",output buffer is disabled and pseudo-open-drain is materialized. ・ PxPUP: Port x pull-up control register To control program pull ups. ・ PxPDN: Port x pull-down control register To control programmable pull downs. ・ PxIE: Port x input control register To control inputs. For avoided through current, default setting prohibits inputs. Page 99 TMPM332FWUG ...
Page 120
... Pin Name I/O Input only Output only Input only Input Output Input Output Input Output Page 100 TMPM332FWUG <DRVE> <DRVE> × × "High" Level Output "High" Level Output ο ο × Depends on PxIE[m] Enabled when data is valid. Disabled when data is invalid. ...
Page 121
... Port A output control register Port A function register 1 Port A pull-up control register Port A pull-down control register Port A input control register − − T9 Register name PADATA PACR PAFR1 PAPUP PAPDN PAIE Page 101 TMPM332FWUG T12 Base Address = 0x4000_0000 Address (Base+) 0x0000 0x0004 0x0008 0x002C 0x0030 0x0038 ...
Page 122
... After reset 0 Bit Bit Symbol Type 31-8 − R 7-4 − R/W 3-0 PA3C-PA0C R Read as 0. Write 0. Port A data register Read as 0. Write 0. Output 0: disable 1: enable Page 102 TMPM332FWUG PA3 PA2 PA1 Function PA3C PA2C PA1C Function PA0 PA0C 1 ...
Page 123
... After reset 0 0 Bit Bit Symbol Type 31-7 − R Read as 0. 6-4 − R/W Write 0. 3 PA3F1 R/W 0: PORT 1: TRACEDATA0 2 PA2F1 R/W 0: PORT 1: TRACECLK 1 PA1F1 R/W 0: PORT 1: SWCLK 0 PA0F1 R/W 0: PORT 1: SWDIO PA3F1 PA2F1 Function Page 103 TMPM332FWUG PA1F1 PA0F1 ...
Page 124
... After reset 0 Bit Bit Symbol Type 31-2 − PA1DN R/W 0 − PA3UP Read as 0. Write 0. Pull-up 0: Disable 1: Enable Read as 0. Pull-up 0:Disable 1:Enable Read as 0. Pull-down 0: Disable 1: Enable Read as 0. Page 104 TMPM332FWUG PA2UP - PA0UP Function PA1DN Function ...
Page 125
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-4 − R/W Write 0. 3-0 PA3IE-PA0IE R/W Input 0: DIsable 1: Enable PA3IE PA2IE Function Page 105 TMPM332FWUG PA1IE PA0IE ...
Page 126
... Port B output control register Port B function register 1 Port B pull-up control register Port B input control register − − − Register name PBDATA PBCR PBFR1 PBPUP PBIE Page 106 TMPM332FWUG − − − T11 Base Address = 0x4000_0040 Address (Base+) 0x0000 0x0004 0x0008 0x002C 0x0038 0 ...
Page 127
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-1 − R/W Write 0. 0 PB0C R/W Output 0: Disable 1: Enable Function Function Page 107 TMPM332FWUG PB0 PB0C ...
Page 128
... PBFR1 (Port B function register 1) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-3 − R 2-1 − R/W 0 PB0F1 R Read as 0. Write 0. 0: PORT 1: SWV Page 108 TMPM332FWUG Function PB0F1 1 ...
Page 129
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-1 − R/W Write 0. 0 PB0IE R/W Input 0: Disable 1: Enable Function Function Page 109 TMPM332FWUG PB0UP PB0IE ...
Page 130
... Port D Register Port D data register Port D function register 1 Port D pull-up control register Port D input control register T17 T17 T17 Register name PDDATA PDFR1 PDPUP PDIE Page 110 TMPM332FWUG T18 T18 T18 Base Address = 0x4000_00C0 Address (Base+) 0x0000 0x0008 0x002C 0x0038 0 T18 ...
Page 131
... After reset 0 0 Bit Bit Symbol Type 31-4 − R Read PD3F1 R/W 0: PORT 1: TB6IN1 2 PD2F1 R/W 0: PORT 1: TB6IN0 1 PD1F1 R/W 0: PORT 1: TB5IN1 0 PD0F1 R/W 0: PORT 1: TB5IN0 PD5 PD4 PD3 Function PD3F1 PD2F1 Function Page 111 TMPM332FWUG PD2 PD1 PD0 PD1F1 PD0F1 ...
Page 132
... PD7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PD7IE-PD0IE R PD6UP PD5UP PD4UP Read as 0. Pull-up 0: Disable 1: Enable PD6IE PD5IE PD4IE Read as 0. Input 0: Disable 1: Enable Page 112 TMPM332FWUG PD3UP PD2UP PD1UP Function PD3IE PD2IE PD1IE Function PD0UP ...
Page 133
... Port E function register 2 Port E open drain control register Port E pull-up control register Port E input control register T10 T4 T16 Base Address = 0x4000_0100 PEDATA PECR PEFR1 PEFR2 PEOD PEPUP PEIE Page 113 TMPM332FWUG T10 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0028 0x002C 0x0038 ...
Page 134
... After reset 0 Bit Bit Symbol Type 31-7 − R 6-0 PE6C-PE0C R PE6 PE5 PE4 Read as 0. Port E data register PE6C PE5C PE4C Read as 0. Output 0: Disable 1: Enable Page 114 TMPM332FWUG PE3 PE2 PE1 Function PE3C PE2C PE1C Function PE0 ...
Page 135
... R Read PE6F1 R/W 0: PORT 1: SCLK1 5 PE5F1 R/W 0: PORT 1: RXD1 4 PE4F1 R/W 0: PORT 1: TXD1 3 PE3F1 R/W 0: PORT 1: RXIN 2 PE2F1 R/W 0: PORT 1: SCLK0 1 PE1F1 R/W 0: PORT 1: RXD0 0 PE0F1 R/W 0: PORT 1: TXD0 PE5F1 PE4F1 PE3F1 Function Page 115 TMPM332FWUG PE2F1 PE1F1 PE0F1 ...
Page 136
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-7 − R 6-0 PE6OD- R/W PE0OD PE6F2 - - Read PORT 1: CTS1 Read PORT 1: CTS0 Read PE6OD PE5OD PE4OD Read CMOS 1: Open-drain Page 116 TMPM332FWUG PE2F2 - Function PE3OD PE2OD PE1OD Function PE0OD 0 ...
Page 137
... After reset bit symbol - PE6IE After reset 0 0 Bit Bit Symbol Type 31-7 − R Read as 0. 6-0 PE6IE-PE0IE R/W Input 0: Disable 1: Enable PE5UP PE4UP PE3UP Function PE5IE PE4IE PE3IE Function Page 117 TMPM332FWUG PE2UP PE1UP PE0UP PE2IE PE1IE PE0IE ...
Page 138
... Port F pull-up control register Port F input control register Note:Access to the "reserved" areas is prohibited T13 T13 T13 Register name PFDATA PFCR PFFR1 − PFOD PFPUP PFIE Page 118 TMPM332FWUG − − − Base Address = 0x4000_0140 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0028 0x002C 0x0038 0 − ...
Page 139
... After reset bit symbol - - After reset bit symbol - PF6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read − R/W Write 0. 6-4 PF6C-PF4C R/W Output 0: Disable 1: Enable 3-0 − R/W Write PF5 PF4 - Function PF5C PF4C - Function Page 119 TMPM332FWUG ...
Page 140
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-8 − − R/W 6 PF6F1 R/W 5 PF5F1 R/W 4 PF4F1 R/W 3-0 − R PF6F1 PF5F1 PF4F1 Read as 0. Write 0. 0: PORT 1: SCK1 0: PORT 1: SI1/SCL1 0: PORT 1: SO1/SDA1 Write 0. Page 120 TMPM332FWUG Function ...
Page 141
... After reset bit symbol - - After reset bit symbol - PF6UP After reset 0 0 Bit Bit Symbol Type 31-8 − R Read − R/W Write 0. 6-4 PF6UP-PF4UP R/W Pull-up 0: Disable 1: Enable 3-0 − R/W Write PF5OD PF4OD - Function PF5UP PF4UP - Function Page 121 TMPM332FWUG ...
Page 142
... After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-8 − − R/W 6-4 PF6IE-PF4IE R/W 3-0 − R PF6IE PF5IE PF4IE Read as 0. Write 0. Input 0: Disable 1: Enable Write 0. Page 122 TMPM332FWUG Function ...
Page 143
... Port G open drain control register Port G pull-up control register Port G input control register Note:Access to the "reserved" areas is prohibited − − T8 T13 Base Address = 0x4000_0180 PGDATA PGCR PGFR1 - PGOD PGPUP PGIE Page 123 TMPM332FWUG 1 0 T13 T13 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x0028 0x002C 0x0038 ...
Page 144
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-8 − R 7-4 - R/W 3-0 PG3C-PG0C R Read as 0. Write 0. Port G data register Read as 0. Write 0. Output 0: Disable 1: Enable Page 124 TMPM332FWUG PG3 PG2 PG1 Function PG3C PG2C PG1C Function PG0 PG0C 0 ...
Page 145
... After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-4 − R/W Write 0. 3 PG3F1 R/W 0: PORT 1: INT4 2 PG2F1 R/W 0: PORT 1: SCK0 1 PG1F1 R/W 0: PORT 1: SI0/SCL0 0 PG0F1 R/W 0: PORT 1: SO0/SDA0 PG3F1 PG2F1 Function Page 125 TMPM332FWUG PG1F1 PG0F1 ...
Page 146
... After reset 0 Bit Bit Symbol Type 31-8 − R 7-4 − R/W 3-0 PG3UP- R/W PG0UP PG3OD Read as 0. Write 0. 0: CMOS 1: Open-drain PG3UP Read as 0. Write 0. Pull-up 0: Disable 1: Enable Page 126 TMPM332FWUG PG2OD PG1OD PG0OD Function PG2UP PG1UP PG0UP Function ...
Page 147
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-4 − R/W Write 0. 3-0 PG3IE-PG0IE R/W Input 0: Disable 1: Enable PG3IE PG2IE Function Page 127 TMPM332FWUG PG1IE PG0IE ...
Page 148
... Port H function register 1 Reserved Port H pull-up control register Port H input control register Note:Access to the "reserved" areas is prohibited − − − Register name PHDATA PHCR PHFR1 − PHPUP PHIE Page 128 TMPM332FWUG Base Address = 0x4000_01C0 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x002C 0x0038 0 T5 ...
Page 149
... After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-4 − R/W Write 0. 3-0 PH3C-PH0C R/W Output 0: Disable 1: Enable PH3 PH2 Function PH3C PH2C Function Page 129 TMPM332FWUG PH1 PH0 PH1C PH0C ...
Page 150
... After reset 0 Bit Bit Symbol Type 31-8 − R 7-4 − R/W 3 PH3F1 R/W 2 PH2F1 R/W 1 PH1F1 R/W 0 PH0F1 R PH3F1 Read as 0. Write 0. 0: PORT 1: TB1IN1 0: PORT 1: TB1IN0 0: PORT 1: TB0IN1 0: PORT 1: TB0IN0 Page 130 TMPM332FWUG PH2F1 PH1F1 Function PH0F1 0 ...
Page 151
... After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-4 − R/W Write 0. 3-0 PH3IE-PH0IE R/W Input 0: Disable 1: Enable PH3UP PH2UP Function PH3IE PH2IE Function Page 131 TMPM332FWUG PH1UP PH0UP PH1IE PH0IE ...
Page 152
... Port I function register 1 Reserved Port I pull-up control register Port I input control register Note:Access to the "reserved" areas is prohibited − Register name PIDATA PICR PIFR1 − PIPUP PIIE Page 132 TMPM332FWUG Base Address = 0x4000_0200 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x002C 0x0038 0 T9 ...
Page 153
... After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-6 − R/W Write 0. 5-0 PI5C-PI0C R/W Output 0: Disable 1: Enable PI5 PI4 PI3 Function PI5C PI4C PI3C Function Page 133 TMPM332FWUG PI2 PI1 PI0 PI2C PI1C PI0C ...
Page 154
... R 7-6 − R/W 5 PI5F1 R/W 4 PI4F1 R/W 3 PI3F1 R/W 2 PI2F1 R/W 1 PI1F1 R/W 0 PI0F1 R PI5F1 PI4F1 Read as 0. Write 0. 0: PORT 1: TB5OUT 0: PORT 1: TB4OUT 0: PORT 1: TB3OUT 0: PORT 1: TB2OUT 0: PORT 1: TB1OUT 0: PORT 1: TB0OUT Page 134 TMPM332FWUG PI3F1 PI2F1 PI1F1 Function PI0F1 0 ...
Page 155
... After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-6 − R/W Write 0. 5-0 PI5IE-PI0IE R/W Input 0: Disable 1: Enable PI5UP PI4UP PI3UP Function PI5IE PI4IE PI3IE Function Page 135 TMPM332FWUG PI2UP PI1UP PI0UP PI2IE PI1IE PI0IE ...
Page 156
... Port J function register 1 Reserved Port J pull-up control register Port J input control register Note:Access to the "reserved" areas is prohibited − − T9 Register name PJDATA PJCR PJFR1 − PJPUP PJIE Page 136 TMPM332FWUG Base Address = 0x4000_0240 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x002C 0x0038 0 T7 ...
Page 157
... After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-5 − R/W Write 0 4-0 PJ4C-PJ0C R/W Output 0 : Disable 1 : Enable PJ4 PJ3 PJ2 Function PJ4C PJ3C PJ2C Function Page 137 TMPM332FWUG PJ1 PJ0 PJ1C PJ0C ...
Page 158
... Bit Bit Symbol Type 31-8 − R 7-5 − R/W 4 PJ4F1 R/W 3 PJ3F1 R/W 2 PJ2F1 R/W 1 PJ1F1 R/W 0 PJ0F1 R PJ4F1 Read as 0. Write 0. 0: PORT 1: TB6OUT 0: PORT 1: INT3 0: PORT 1: INT2 0: PORT 1: INT1 0: PORT 1: INT0 Page 138 TMPM332FWUG PJ3F1 PJ2F1 PJ1F1 Function PJ0F1 0 ...
Page 159
... After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-5 − R/W Write 0. 4-0 PJ4IE-PJ0IE R/W Input 0: Disable 1: Enable PJ4UP PJ3UP PJ2UP Function PJ4IE PJ3IE PJ2IE Function Page 139 TMPM332FWUG PJ1UP PJ0UP PJ1IE PJ0IE ...
Page 160
... Port K function register 1 Port K function register 2 Port K pull-up control register Port K input control register − − − Register name PKDATA PKCR PKFR1 PKFR2 PKPUP PKIE Page 140 TMPM332FWUG − − T15 T14 Base Address = 0x4000_0280 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x002C 0x0038 0 ...
Page 161
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-3 − R Read − R/W Write 0. 1-0 PK1C-PK0C R/W Output 0: Disable 1: Enable Function Function Page 141 TMPM332FWUG PK1 PK0 PK1C PK0C ...
Page 162
... After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-3 − − R/W 1 PK1F1 R/W 0 PK0F1 R Read as 0. Write 0. 0: PORT 1: SCOUT 0: PORT 1: CEC Page 142 TMPM332FWUG PK1F1 Function PK0F1 0 ...
Page 163
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-3 − R Read − R/W Write 0. 1 PK1UP R/W Pull-up 0: Disable 1: Enable 0 − R Read Function Function Page 143 TMPM332FWUG PK1F2 - PK1UP - ...
Page 164
... After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-3 − − R/W 1-0 PK1IE-PK0IE R Read as 0. Write 0. Input 0: Disable 1: Enable Page 144 TMPM332FWUG PK1IE Function PK0IE 0 ...
Page 165
... Output − R − Input − R − − ο R − − ο R − Page 145 TMPM332FWUG Programma- ble Note open-drain − ο BOOT input enabled during − reset − − ο − ο Function output triggered by − enable signal Function output triggered by − ...
Page 166
... Block Diagrams of Ports 8.3.2 Type T3 (Function Control) Function Input Drive Disable in STOP Mode (Set by <DRVE>) PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 PxDATA (Output Latch) PxIE (Input Control Port Read Figure 8-1 Port Type T3 Page 146 TMPM332FWUG RESET I/O Port ...
Page 167
... Type T4 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open Drain Control) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode Set by <DRVE> Figure 8-2 Port Type T4 Page 147 TMPM332FWUG RESET I/O Port ...
Page 168
... Block Diagrams of Ports 8.3.4 Type5 T5 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Function Input BOOT Drive Disable in STOP Mode (Set by <DRVE> Figure 8-3 Port Type T5 Page 148 TMPM332FWUG RESET I/O Port ...
Page 169
... Type T6 PxPDN (Pull-down Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode (Set by <DRVE> Figure 8-4 Port Type T6 Page 149 TMPM332FWUG RESET I/O Port ...
Page 170
... Block Diagrams of Ports 8.3.6 Type T7 Interrupt Input Drive Disable In STOP Mode (Set by <DRVE>) PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control Port Read Noise Filter ( ) Figure 8-5 Port Type T7 Page 150 TMPM332FWUG RESET I/O Port ...
Page 171
... Type T8 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Interrupt Noise Filter Input ( ) Drive Disable In STOP Mode Set by <DRVE> Figure 8-6 Port Type T8 Page 151 TMPM332FWUG RESET I/O Port ...
Page 172
... Block Diagrams of Ports 8.3.8 Type T9 (Pull-up Control) (Output Control) (Function Control) (Output Latch) (Input Control) Port Read Drive Disable In STOP Mode (Set by <DRVE> PxPUP PxCR PxFR1 1 Function Output PxDATA 0 PxIE 0 1 Figure 8-7 Port Type T9 Page 152 TMPM332FWUG RESET I/O Port ...
Page 173
... Type T10 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Drive Disable in STOP Mode (Set by <DRVE>) 1 Function Output Figure 8-8 Port Type T10 Page 153 TMPM332FWUG RESET I/O Port ...
Page 174
... Control) (Output Control) (Function Control) (Output Latch) (Input Control) Port Read Drive Disable in STOP Mode (Set by <DRVE>) PxPUP PxCR Function Output Enable 1 0 PxFR1 1 Function Output PxDATA 0 PxIE 0 1 Figure 8-9 Port Type T11 Page 154 TMPM332FWUG RESET I/O Port ...
Page 175
... PxPUP (Pull-up Control) PxCR (Output Control) Function Output Enable PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE> Function 1 Output Figure 8-10 Port Type T12 Page 155 TMPM332FWUG RESET I/O Port ...
Page 176
... PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE>) 1 Function Output Figure 8-11 Port Type T13 Page 156 TMPM332FWUG RESET I/O Port ...
Page 177
... Type T14 PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE>) Function 1 Output N-chanel 0 Open-drain 0 1 Figure 8-12 Port Type T14 Page 157 TMPM332FWUG RESET I/O Port ...
Page 178
... Control) PxCR (Output Control) PxFR2 (Function Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Drive Disable in STOP Mode Set by <DRVE> Function 1 Function 1 Output2 Output1 0 0 Figure 8-13 Port Type T15 Page 158 TMPM332FWUG RESET I/O Port ...
Page 179
... Control) PxFR2 (Function Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Function Input1 Function Input2 Drive Disable in STOP Mode Set by <DRVE> Function 1 Output1 Figure 8-14 Port Type T16 Page 159 TMPM332FWUG RESET I/O Port ...
Page 180
... Block Diagrams of Ports 8.3.16 Type T17 Analog Input Drive Disable in STOP Mode PxPUP (Pull-up Control) PxIE (Input Control) Port Read Figure 8-15 Port Type T17 Page 160 TMPM332FWUG <DRVE> RESET Input Port ...
Page 181
... Type T18 PxPUP (Pull-up Control) PxFR1 (Function Control) PxIE (Input Control) Port Read Function Input Analog Input Drive Disable in STOP Mode Set by <DRVE>) Figure 8-16 Port TypeT18 Page 161 TMPM332FWUG RESET I/O Port ...
Page 182
... SWDIO(I/O) ・ Input Port T6 Output Port SWCLK (Input) ・ Input Port T9 Output Port TRACECLK (Output) Input Port T9 Output Port TRACEDATA0(Output) Port After re- Function set Type Input Port T11 Output Port SWV (Output) ・ Page 162 TMPM332FWUG PACR PAFR1 PAPUP PAPDN PAIE ...
Page 183
... Input Port 0 TB5IN1(Input) 1 Analog Input x ・ Input Port 0 TB6IN0(Input) 1 Analog Input x ・ Input Port 0 TB6IN1(Input) 1 Analog Input ・ x Input Port 0 Analog Input x ・ Input Port 0 Analog Input x ・ Input Port 0 Analog Input ・ x Input Port 0 Analog Input x ・ Page 163 TMPM332FWUG PDIE ...
Page 184
... Input Port 0 Output Port 1 RXD0(Input) 0 Input Port 0 Output Port 1 SCLK0(Input) 0 SCLK0(Output) 1 CTS0(Input) 0 Input Port 0 Output Port 1 RXIN(Input) 0 Input Port 0 Output Port 1 TXD1(Output) 1 Input Port 0 Output Port 1 RXD1(Input) 0 Input Port 0 Output Port 1 SCLK1(Input) 0 SCLK1(Output) 1 CTS1(Input) 0 Page 164 TMPM332FWUG PEFR1 PEFR2 PEOD PEPUP PEIE ...
Page 185
... Input Port Output Port PG1 T13 SI0(Input) SCL0(Input/Output) Input Port Output Port PG2 T13 SCK0(Input) SCK0(Output) Input Port PG3 T8 Output Port INT4(Input) After re- PFCR PFFR1 PFFR2 set After re- Function PGCR PGFR1 set Page 165 TMPM332FWUG PFOD PFPUP PFIE PGOD PGPUP PGIE ...
Page 186
... After re- Function set Type Input Port T9 Output Port TB0OUT(Output) Input Port T9 Output Port TB1OUT(Output) Input Port T9 Output Port TB2OUT(Output) Input Port T9 Output Port TB3OUT(Output) Input Port T9 Output Port TB4OUT(Output) Input Port T9 Output Port TB5OUT(Output) Page 166 TMPM332FWUG PHCR PHFR1 PHPUP PHIE ...
Page 187
... Input Port PK0 T14 Output Port CEC (Input/Output) Input Port Output Port PK1 T15 SCOUT (Output) ALARM (Output) Note:PK0 is an N-ch open drain port. After re- Function PJCR PJFR1 set After re- Function PKCR PKFR1 set Page 167 TMPM332FWUG PJPUP PJIE PKFR2 PKPUP PKIE ...
Page 188
... Appendix (Port setting List) Page 168 TMPM332FWUG ...
Page 189
... Timer synchronous mode The use of the capture function allows TMRB to perform the following three measurements. ・ Frequency measurement ・ Pulse width measurement ・ Time difference measurement In the following explanation of this section, "x" indicates a channel number. Page 169 TMPM332FWUG ...
Page 190
... Differences in the Specifications 9.2 Differences in the Specifications TMPM332FWUG contains 10-channel of TMRB. Each channel functions independently and the channels operate in the same way except for the differences in their specification as shown in Table 9-1. Some of the channels can put the capture trigger and the synchronous start trigger on other channels. ...
Page 191
... Figure 9-1 TMRBx Block Diagram( Register 1 interrupt output Register 0 interrupt output Overflow interrupt output Register 1 interrupt mask Register 0 interrupt mask Overflow interrupt mask Page 171 TMPM332FWUG ...
Page 192
... Base Address 0x4001_0000 0x4001_0040 0x4001_0080 0x4001_00C0 0x4001_0100 0x4001_0140 0x4001_0180 0x4001_01C0 0x4001_0200 0x4001_0240 Register name(x TBxEN TBxRUN TBxCR TBxMOD TBxFFCR TBxST TBxIM TBxUC TBxRG0 TBxRG1 TBxCP0 TBxCP1 Page 172 TMPM332FWUG Address(Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C ...
Page 193
... TMRB module. This can reduce power consumption. (This disables reading from and writing to the other reg- isters except TBxEN register.) To use the TMRB, enable the TMRB operation (set to "1") before programming each register in the TMRB module. If the TMRB operation is executed and then disabled, the settings will be maintained in each register. 6-0 − R Read Function Page 173 TMPM332FWUG ...
Page 194
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-3 − TBPRUN R/W 1 − TBRUN R Read as 0. Prescaler operation 0: Stop & clear 1: Count Read as 0. Count operation 0: Stop & clear 1: Count Page 174 TMPM332FWUG TBPRUN - TBRUN Function ...
Page 195
... Type 31-8 − R Read TBWBF R/W Double Buffer 0: Disabled 1: Enabled 6 − R/W Write 0. 5 TBSYNC R/W Synchronous mode switching 0: individual (unit of channel) 1: synchronous 4 − R Read I2TB R/W Operation at IDLE mode 0: Stop 1:Operation 2-0 − R Read TBSYNC - I2TB Function Page 175 TMPM332FWUG ...
Page 196
... Enables clearing of the up-counter. Clears and controls the up-counter. When "0" is written, it disables clearing of the up-counter. When "1" is written, it clears up counter when there is a match with Timer Regsiter1 (TBxRG1). Selects the TMRBx source clock. 00: TBxIN0 pin input 01: φT1 10: φT4 11: φT16 Page 176 TMPM332FWUG ...
Page 197
... By setting "1", the timer-flip-flop reverses when an up-counter value is matched with the Timer register 0 (TBxRG0). 1-0 TBFF0C[1:0] R/W TBxFF0 control 00: Invert Reverses the value of TBxFF0 (reverse by using software). 01: Set Sets TBxFF0 to "1". 10: Clear Clears TBxFF0 to "0". 11: Don't care * This is always read as "11" TBC1T1 TBC0T1 TBE1T1 Function Page 177 TMPM332FWUG TBE0T1 TBFF0C ...
Page 198
... TBxRG1 When a match with the timer register 1 (TBxRG1) is detected,"1" is set. Match flag (TBxRG0) 0:No match is detected 1:Detects a match with TBxRG0 When a match with the timer register 0 (TBxRG0) is detected, "1" is set. Page 178 TMPM332FWUG ...
Page 199
... After reset bit symbol After reset 0 0 Bit Bit Symbol Type 31-16 − R Read as 0. 15-0 TBUC[15:0] R Captures a value by reading up-counter out. If TBxUC is read, current up-counter value can be captured TBIMOF Function TBUC TBUC Function Page 179 TMPM332FWUG TBIM1 TBIM0 ...
Page 200
... After reset 0 7 bit symbol After reset 0 Bit Bit Symbol Type 31-16 − R 15-0 TBRG1[15:0] R TBRG0 TBRG0 Read as 0. Sets a value comparing to the up-counter TBRG1 TBRG1 Read as 0. Sets a value comparing to the up-counter. Page 180 TMPM332FWUG Function Function ...