ZLF645E0P2832G Zilog, ZLF645E0P2832G Datasheet - Page 135

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ZLF645E0P2832G

Manufacturer Part Number
ZLF645E0P2832G
Description
Microcontrollers (MCU) 32K Flash 1K RAM 28 pin
Manufacturer
Zilog
Datasheet

Specifications of ZLF645E0P2832G

Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
1 KB
Interface Type
ICP, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Package / Case
PDIP-28
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
 Details
Table 66. Interrupt Mask Register (IMR)
PS026407-0408
Bit
Field
Reset
R/W
Address
Bit Position
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Interrupt Mask Register
Master Interrupt
Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When
reset, all interrupts are disabled. When writing 1 to bit 7, you must also execute the EI
instruction to enable interrupts (see
Value
Enable
R/W
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
7
0
Description
Master Interrupt Enable
Use only DI and EI instructions to alter this bit. Always disable interrupts (DI
instruction) before writing this register.
All interrupts are disabled.
Interrupts are enabled/disabled individually in bits [5:0].
Reserved
Reads are undefined; Must be written to 1.
Disables IRQ5.
Enables IRQ5.
Disables IRQ4.
Enables IRQ4.
Disables IRQ3.
Enables IRQ3.
Disables IRQ2.
Enables IRQ2.
Disables IRQ1.
Enables IRQ1.
Disables IRQ0.
Enables IRQ0.
Reserved
X
6
Bank Independent: FBh; Linear: 0FBh
Enable
IRQ5
R/W
X
5
Table
Enable
IRQ4
R/W
X
4
66).
Enable
IRQ3
R/W
X
3
ZLF645 Series Flash MCUs
Enable
IRQ2
R/W
X
2
Product Specification
Interrupt Mask Register
Enable
IRQ1
R/W
X
1
Enable
IRQ0
R/W
X
0
127

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