Z8623012SSC00TR Zilog, Z8623012SSC00TR Datasheet - Page 32

• Manufacturer Part Number: Z8623012SSC00TR
• Description: IC SMART VCHIP 18SOIC
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8623012SSC00TR

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply, Analog: -

6.1.12 Content Advisory Register 2
6.1.13 Blocking Control Register 1
6.1.14 Content Advisory Ratings Select 5
32
C
ONTROL
D
byte of the received Content Advisory Ratings packet.
D
the data from the received Content Advisory packet matches the user selection
contained in one of the Content Advisory Ratings registers, and the
the blocking status.
T
D
byte of the received Content Advisory Ratings packet.
D
packet. When this bit is High, it indicates that the data from the received Content
Advisory packet is valid. This bit clears if no Content Advisory packet is received
after 5 seconds.
T
D
of the blocking signal on a change of channel. The default value of
time of 2 seconds. The time is extended in 2 frames with each binary step.
D
BLEN=1
This register holds the Canadian English Language Content Advisory selections
made by the viewer.
T
Bit
R/W
Bit
R/W
Bit
R/W
ABLE
ABLE
ABLE
0
7
0
7
0
7
R
-D
-B.
-D
-P.
-D
-BLEN.
EGISTERS
6
6
6
.
.
This bit indicates the validity of the data in the recovered Content Advisory
-BTE.
This bit indicates the blocking status. When this bit is High, it indicates that
23. C
24. B
25. C
These bits hold the corresponding information recovered from the first
These bits hold the corresponding information recovered from the second
disables blocking.
These bits enable the blocking capability.
ONTENT
LOCKING
These bits set the Block Timer which controls the duration of the hold
ONTENT
BLEN
R/W
res
Z86230—PRELIMINARY
P
R
R
7
7
7
A
A
C
DVISORY
DVISORY
ONTROL
R/W
R/W
18+
R
6
1
6
6
R
R
R
EGISTER
EGISTER
ATINGS
(F)V
R/W
R/W
14+
R
5
5
5
S
1 (A
2 (A
R/W
R/W
ELECT
PG
S
R
4
4
4
DDRESS
DDRESS
R
EGISTER
R/W
R/W
BTE
G
R
3
L
3
3
BLEN=0
= 0Eh)
= 0Dh)
5 (A
R/W
R/W
C8+
g2
R
2
2
2
PS000401-TVC0699
enables blocking;
DDRESS
R
EGISTERS
R/W
R/W
0
PB
g1
R
C
1
1
1
has a hold
= 0Fh)
pin is in
S
UMMARY
R/W
R/W
g0
R
E
0
0
0