AD1896AYRS Analog Devices Inc, AD1896AYRS Datasheet - Page 19

• Manufacturer Part Number: AD1896AYRS
• Description: IC CONV SAMPLE RATE ASYNC 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1896AYRS

• Rohs Status: RoHS non-compliant
• Applications: Automotive Audio, processing, receivers
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Not Compliant

HARDWARE MODEL
The output rate of the low-pass filter of Figure 5 would be the
interpolation rate, 2
a rate of 201.3 GHz is clearly impractical, not to mention the
number of taps required to calculate each interpolated sample.
However, since interpolation by 2
samples between each f
the low-pass FIR filter are by zero. A further reduction can be
realized by the fact that since only one interpolated sample is
taken at the output at the f
needs to be performed per f
lutions. A 64-tap FIR filter for each f
to suppress the images caused by the interpolation.
The difficulty with the above approach is that the correct inter-
polated sample needs to be selected upon the arrival of f
Since there are 2
arrival of the f
of 1/201.3 GHz = 4.96 ps. Measuring the f
clock of 201.3 GHz frequency is clearly impossible; instead,
several coarse measurements of the f
and averaged over time.
Another difficulty with the above approach is the number of
coefficients required. Since there are 2
with a 64-tap FIR filter, there needs to be 2
cients for each tap, which requires a total of 2
reduce the amount of coefficients in ROM, the AD1896 stores a
small subset of coefficients and performs a high order interpola-
tion between the stored coefficients. So far the above approach
works for the case of f
the output sample rate, f
rate, f
of the convolution must be scaled. As the input sample rate
rises over the output sample rate, the antialiasing filter’s cutoff
frequency has to be lowered because the Nyquist frequency of
REV. A
IN
Figure 6. Frequency Domain of the Interpolation and
Resampling
f
S_IN
S_IN
FREQUENCY DOMAIN OF SAMPLES AT f
FREQUENCY DOMAIN OF THE INTERPOLATION
FREQUENCY DOMAIN OF f
FREQUENCY DOMAIN AFTER
RESAMPLING
, the ROM starting address, input data, and the length
SIN(X)/X OF ZERO-ORDER HOLD
INTERPOLATE
S_OUT
BY N
20
possible convolutions per f
20
clock must be measured with an accuracy
S_OUT
¥ 192000 kHz = 201.3 GHz. Sampling at
S_IN
S_OUT
S_OUT
> f
sample, most of the multiplies in
LOW-PASS
S_OUT
S_OUT
, is less than the input sample
FILTER
S_IN
RESAMPLING
20
rate, only one convolution
. However, in the case when
period instead of 2
involves zero-stuffing 2
S_OUT
S_OUT
20
S_IN
2
possible convolutions
20
ZERO-ORDER
clock period are made
sample is sufficient
S_OUT
20
f
S_IN
HOLD
26
S_OUT
polyphase coeffi-
2
20
2
f
S_IN
coefficients. To
20
period with a
f
S_IN
f
period, the
S_IN
20
S_OUT
f
S_OUT
convo-
20
OUT
– 1
.
–19–
the output samples is less than the Nyquist frequency of the
input samples. To move the cutoff frequency of the antialiasing
filter, the coefficients are dynamically altered and the length
of the convolution is increased by a factor of (f
This technique is supported by the Fourier transform property
that if f(t) is F(w), then f(k ¥ t) is F(w/k). Thus, the range of
decimation is simply limited by the size of the RAM.
THE SAMPLE RATE CONVERTER ARCHITECTURE
The architecture of the sample rate converter is shown in
Figure 7. The sample rate converter’s FIFO block adjusts the
left and right input samples and stores them for the FIR filter’s
convolution cycle. The f
to the FIFO block and the ramp input to the digital servo
loop. The ROM stores the coefficients for the FIR filter convo-
lution and performs a high order interpolation between the
stored coefficients. The sample rate ratio block measures the
sample rate for dynamically altering the ROM coefficients and
scaling of the FIR filter length as well as the input data. The
digital servo loop automatically tracks the f
sample rates and provides the RAM and ROM start addresses
for the start of the FIR filter convolution.
The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample rate
converter and the scaling of the input data by the sample rate
ratio before storing the samples in the RAM. The input data is
scaled by the sample rate ratio because as the FIR filter length
of the convolution increases, so does the amplitude of the
convolution output. To keep the output of the FIR filter from
saturating, the input data is scaled down by multiplying it by
(f
data for muting and unmuting of the AD1896.
The RAM in the FIFO is 512 words deep for both left and right
channels. An offset to the write address provided by the f
counter is added to prevent the RAM read pointer from ever
overlapping the write address. The offset is selectable by the
GRPDLYS, group delay select, signal. A small offset, 16, is
added to the write address pointer when GRPDLYS is high,
and a large offset, 64, is added to the write address pointer when
GRPDLYS is low. Increasing the offset of the write address pointer
is useful for applications when small changes in the sample rate
ratio between f
mation rate can be calculated from the RAM word depth and
GRPDLYS as (512 – 16)/64 taps = 7.75 for short group delay and
(512 – 64)/64 taps = 7 for long group delay.
S_OUT
Figure 7. Architecture of the Sample Rate Converter
RIGHT DATA IN
LEFT DATA IN
COUNTER
/f
S_IN
f
S_IN
) when f
f
S_OUT
f
S_IN
S_IN
and f
S_OUT
SAMPLE RATE RATIO
SAMPLE RATE
SERVO LOOP
S_OUT
S_IN
DIGITAL
RATIO
FIFO
< f
counter provides the write address
S_IN
are expected. The maximum deci-
. The FIFO also scales the input
EXTERNAL
RATIO
ROM A
ROM B
ROM C
ROM D
S_IN
FIR FILTER
and f
AD1896
S_IN
L/R DATA OUT
HIGH
ORDER
INTERP
/f
S_OUT
S_OUT
).
S_IN