HSDL-7001 Lite-On Electronics, HSDL-7001 Datasheet - Page 4

IC ENCODER/DECODER IRDA 16-SOIC

HSDL-7001

Manufacturer Part Number
HSDL-7001
Description
IC ENCODER/DECODER IRDA 16-SOIC
Manufacturer
Lite-On Electronics
Type
Infrared Encoder/Decoderr
Datasheet

Specifications of HSDL-7001

Applications
Fax, Modems, Pagers
Voltage - Supply, Analog
2.7 V ~ 5.5 V
Voltage - Supply, Digital
2.7 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
16-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
516-1276-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HSDL-7001
Manufacturer:
AGILENT
Quantity:
649
Part Number:
HSDL-7001
Manufacturer:
ST
0
Part Number:
HSDL-7001
Manufacturer:
AGILENT
Quantity:
20 000
Company:
Part Number:
HSDL-7001
Quantity:
2 048
Part Number:
HSDL-7001#100
Manufacturer:
AVAGO
Quantity:
248
Part Number:
HSDL-7001#100
Manufacturer:
ST
0
4
Encoding Scheme
The encoding scheme relies on a clock
being present, which is set to 16 times
the data transmission baud rate
(16XCLX). The encoder sends a pulse
for every space or “0” that is sent on
the TXD line. On a high to low
transition of the TXD line, the
generation of the pulse is delayed for
Decoding Scheme
The IrDA-SIR (Serial InfraRed)
decoding modulation method can be
thought of as a pulse stretching
scheme.
Every high to low transition of the
IR_RXD line signifies the arrival of a
pulse. This pulse needs to be
16XCLK
IRRXD
RXD
16XCLK
TXD
IRTXD
16 CYCLES
7 CS
16 CYCLES
3 CS
16 CYCLES
16 CYCLES
3 CS
7 clock cycles of the 16XCLK before
the pulse is set high for 3 clock cycles
(or 3/16th of a bit time) and then
subsequently pulled low. This
generates a 3/16th bit time pulse
centered around the bit of infor-
mation (“0”) that is being transmitted.
stretched to accommodate 1 bit time
(or 16 16XCLK cycles). Every pulse that
is received is translated into a “0” or
space on the RXD line equal to 1 bit
time.
Note 1: The stretched pulse must be
at least 3/4 of a bit time in duration to
be correctly interpreted by a UART.
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
For consecutive spaces, pulses with a
1 bit time delay are generated in
series. If a logic 1 (mark) is sent then
the encoder does not generate a
pulse.
Note 2: It is recommended that TXD
remains high when not transmitting.
This ensures the LED is off and will
not interfere with signal reception.

Related parts for HSDL-7001