ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 11

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
3, 10, 24, 34, 57
32, 37, 43, 45
4, 11
23, 58
40
31
35, 36, 46–49
1, 12, 13, 27, 28, 33,
50, 55, 56
26, 25, 19, 18, 17,
16, 15, 14, 8, 7, 6, 5,
62, 61, 60, 59
2
64
63
53
54
52
51
20
22
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
AIN1–AIN6
NC
P0–P15
HS
VS
FIELD
SDA
SCLK
ALSB
RESET
LLC
XTAL
DVDDIO
DVDDIO
NC = NO CONNECT
DGND
DGND
SFL
P11
P10
NC
NC
NC
HS
P9
P8
P7
P6
P5
Type
G
G
P
P
P
P
I
O
O
O
O
I/O
I
I
I
O
I
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
64
17
PIN 1
INDICATOR
Analog Video Input Channels.
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
No Connect Pins.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
I
I
This pin selects the I
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7181 circuitry.
This is a line-locked output clock for the pixel data output by the ADV7181. Nominally
27 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
2
2
63
18
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input (Max Clock Rate of 400 kHz).
Figure 4. 64-Lead LFCSP/LQFP Pin Configuration
62
19
61
20
60
21
Rev. B | Page 11 of 104
59
22
(Not to Scale)
58
23
ADV7181
TOP VIEW
57
24
2
C address for the ADV7181. ALSB set to a Logic 0 sets the address for a
56
25
55
26
54
27
53
28
52
29
51
30
50
31
49
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AIN5
AIN4
AIN3
AGND
CAPC2
AGND
CML
REFOUT
AVDD
CAPY2
CAPY1
AGND
AIN2
AIN1
DGND
NC
ADV7181