CS493105-CLZ Cirrus Logic Inc, CS493105-CLZ Datasheet - Page 16

• Manufacturer Part Number: CS493105-CLZ
• Description: IC DECODER AUD MULTI STD 44PLCC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Decoderr

Specifications of CS493105-CLZ

• Applications: DVD
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 2.63 V
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1670

1.11.
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
Notes:. 1. The specification f
16
SCCLK clock frequency
Bus free time between transmissions
Start-condition hold time (prior to first clock pulse)
Clock low time
Clock high time
SCDIO setup time to SCCLK rising
SCDIO hold time from SCCLK falling
Rise time of SCCLK
Fall time of SCCLK
Time from SCCLK falling to CS493XX ACK
Time from SCCLK falling to SCDIO valid during read operation
Time from SCCLK rising to INTREQ rising
Hold time for INTREQ from SCCLK rising
Rise time for INTREQ
Setup time for stop condition
Switching Characteristics — I
2. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by
3. This rise time is shorter than that recommended by the I
4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the
5. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next
6. With a 3.3k Ohm pull-up resistor this value is typically 260ns. As this pin is open drain adjusting the pull
7. This time is by design and not tested.
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user’s manual should be consulted for the software speed limitations.
design and not tested.
Section 6.1, “Serial Communication” on page 36.
last data bit of the last byte of data during a read operation as shown.
rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat
this condition as a new read transaction. Send a new start condition followed by the 7-bit address and
the R/W bit (set to 1 for a read). This time is by design and is not tested.
up value will affect the rise time.
scl
Parameter
indicates the maximum speed of the hardware. The system designer should be
2
C
(Note 3), (Note 7)
®
Control Port
(Note 1)
(Note 2)
(Note 4)
(Note 5)
(Note 6)
(Note 7)
L
2
C specifications. For more information, see
= 20 pF)
Symbol
t
t
t
t
t
scsdv
t
t
t
t
t
t
susp
f
hdst
high
scrh
sud
hdd
sca
scrl
CS49300 Family DSP
low
buf
t
scl
t
t
rr
r
f
Min
250
4.7
4.0
1.2
1.0
4.7
0
0
Max
400
300
200
50
40
40
**
DS339F7
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns