STA015$ STMicroelectronics, STA015$ Datasheet - Page 42
![DECODER AUDIO MPEG 2.5 28-SOIC](/photos/6/56/65690/stmicroelectronics-28-soic_sml.jpg)
STA015$
Manufacturer Part Number
STA015$
Description
DECODER AUDIO MPEG 2.5 28-SOIC
Manufacturer
STMicroelectronics
Type
Audio Decoderr
Datasheet
1.STA015T.pdf
(56 pages)
Specifications of STA015$
Applications
Sound Cards, Players, Recorders
Voltage - Supply, Digital
2.4 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply, Analog
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
STA015
ADC_CONF
Address: 0xBC (188)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
Using this register the ADC input interface can be configured as follow:
AIIS: ADC I
ADC: ADC Data Config.
ASCP: ADC Serial Clock Polarity
ALRCP: ADC Left/Right Clock Polarity
ALRCS: ADC Left/Right Clock Start value. This two
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ALRCP
MSB
b7
X
0
1
0
1
0 = sample word must be aligned with LRCK (no I
1 = sample word not aligned with LRCK (I
0 = sample word is LSB first
1 = sample word is MSB first
0 = Data is sampled on rising edge
1 = Data is sampled an falling edge
bits permit to determine Left/Right clock
usage according to the following table:
2
S mode
LRCK
DATA
ALRCS
b6
X
0
0
1
1
DATA 0
b5
X
(Data1, Data2)
DATA 1
ALRCS
(0, 1)
(0, 1)
(1, 2)
b4
2
S compliant mode)
DATA 2
ALRCP
LEFT/RIGHT COUPLE
2
S mode)
b3
DATA 3
D99AU1065
ASCP
b2
DATA 4
(Data3, Data4)
(2, 3)
(2, 3)
(3, 4)
ADC
b1
LSB
AIIS
b0