LTC1064CSW#PBF Linear Technology, LTC1064CSW#PBF Datasheet - Page 7

• Manufacturer Part Number: LTC1064CSW#PBF
• Description: IC FILTR BUILDNG BLK QUAD 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1064CSW#PBF

• Filter Type: Universal Switched Capacitor
• Frequency - Cutoff Or Center: 140kHz
• Number Of Filters: 4
• Max-order: 8th
• Voltage - Supply: ±2.375 V ~ 8 V
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS
ANALOG CONSIDERATIONS
Grounding and Bypassing
The LTC1064 should be used with separated analog and
digital ground planes and single point grounding
techniques.
Pin 6 (AGND) should be tied directly to the analog ground
plane.
Pin 7 (V
0.1µF ceramic capacitor with leads as short as possible.
Pin 19 (V
capacitor. For single supply applications, V
the analog ground plane.
For good noise performance, V
noise and ripple.
All analog inputs should be referenced directly to the
single point ground. The clock inputs should be shielded
from and/or routed away from the analog circuitry and a
separate digital ground plane used.
+
GROUND
ANALOG
) should be bypassed to the ground plane with a
PLANE
–
) should be bypassed with a 0.1µF ceramic
U
7.5V
CERAMIC
0.1µF
INFORMATION
U
+
Figure 2. Example Ground Plane Breadboard Technique for LTC1064
and V
W
–
10
11
12
1
2
3
4
5
6
7
8
9
must be free of
–
can be tied to
PIN 1 IDENT
LTC1064
U
24
23
22
21
20
19
18
17
16
15
14
13
–7.5V
Figure 2 shows an example of an ideal ground plane
design for a 2-sided board. Of course this much ground
plane will not always be possible, but users should strive
to get as close to this as possible. Protoboards are not
recommended.
Buffering the Filter Output
When driving coaxial cables and 1× scope probes, the
filter output should be buffered. This is important espe-
cially when high Qs are used to design a specific filter.
Inadequate buffering may cause errors in noise, distor-
tion, Q and gain measurements . When 10 × probes are
used, buffering is usually not required. An inverting buffer
is recommended especially when THD tests are per-
formed. As shown in Figure 3, the buffer should be
adequately bypassed to minimize clock feedthrough.
NOTE: CONNECT ANALOG AND DIGITAL
GROUND PLANES AT A SINGLE POINT AT
THE BOARD EDGE
5k
0.1µF CERAMIC
V
FOR BEST HIGH FREQUENCY RESPONSE
PLACE RESISTORS PARALLEL TO DOUBLE-
SIDED COPPER CLAD BOARD AND LAY FLAT
(4 RESISTORS SHOWN HERE TYPICAL)
IN
GROUND
DIGITAL
PLANE
CLOCK
(SINGLE POINT
GROUND)
LTC1064
1064 F02
1064fb
7