CAT9554WI-GT2 ON Semiconductor, CAT9554WI-GT2 Datasheet - Page 6

• Manufacturer Part Number: CAT9554WI-GT2
• Description: IC I/O EXPANDER I2C 8B 16SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT9554WI-GT2

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9554WI-GT2; CAT9554WI-GT2TR

CAT9554, CAT9554A
PIN DESCRIPTION
SCL: Serial Clock
The serial clock input clocks all data transferred into
or out of the device. The SCL line requires a pull-up
resistor if it is driven by an open drain output.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs. A pull-
up resistor must be connected from SDA line to V
The value of the pull-up resistor, R
based on minimum and maximum values from Figure
2 and Figure 3 (see Note).
Note: According to the Fast Mode I²C bus specification, for bus capacitance up to 200pF, the pull up device can
be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA)
or a switched resistor circuit.
Doc. No. MD-9002 Rev. F
Figure 2. Minimum R
2.5
1.5
0.5
2
1
0
2
2.4 2.8 3.2 3.6
I OL = 3mA @ V OLmax
Supply Voltage
V CC (V)
P
4
Value versus
P
4.4 4.8 5.2 5.6
, can be calculated
CC
.
6
A0, A1, A2: Device Address Inputs
These inputs are used for extended addressing
capability. The A0, A1, A2 pins should be hardwired to
V
CAT9554/9554As may be addressed on a single bus
system. The levels on these inputs are compared with
corresponding bits, A2, A1, A0, from the slave
address byte.
I/O
Any of these pins may be configured as input or
output. The simplified schematic of I/O
shown in Figure 4. When an I/O is configured as an
input, the Q1 and Q2 output transistors are off
creating a high impedance input with a weak pull-up
resistor (typical 100kΩ). If the I/O pin is configured as
an output, the push-pull output stage is enabled. Care
should be taken if an external voltage is applied to an
I/O pin configured as an output due to the low
impedance paths that exist between the pin and either
V
CC
CC
0
or V
to I/O
or
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Figure 3. Maximum R
SS
7
.
V
: Input / Output Ports
SS
50
Fast Mode I²C Bus / tr max - 300ns
.
100
When
Bus Capacitance
150
C BUS (pF)
Characteristics subject to change without notice
hardwired,
200
P
250
Value versus
© 2008 SCILLC. All rights reserved
300
up
350
0
to I/O
to
400
eight
7
is