MAX7321ATE+T Maxim Integrated Products, MAX7321ATE+T Datasheet - Page 8
![IC I/O EXPANDER I2C 8B 16TQFN-EP](/photos/6/66/66625/16-tqfn_exp_pad_21-0136_sml.jpg)
MAX7321ATE+T
Manufacturer Part Number
MAX7321ATE+T
Description
IC I/O EXPANDER I2C 8B 16TQFN-EP
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX7321ATE.pdf
(17 pages)
Specifications of MAX7321ATE+T
Interface
I²C
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Includes
POR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in applications in which there is legitimate bus activity
during power-up. Also, if SDA and SCL are terminated
with pullup resistors to a different supply voltage than
the MAX7321’s supply voltage, and if that pullup supply
rises later than the MAX7321’s supply, then SDA or
SCL may appear at power-up to be connected to GND.
In such applications, use the four address combina-
tions that are selected by connecting address inputs
AD2 and AD0 to V+ or GND (shown in bold in
These selections are guaranteed to be correct at
power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, an
unexpected combination of pullups might be asserted
until the first I
sarily the MAX7321) is put on the bus, and an unex-
pected combination of ports may initialize as logic-low
outputs instead of inputs or logic-high outputs.
I
Table 3. MAX7321 Address Map
8
2
PIN CONNECTION
GND
GND
GND
GND
AD2
SDA
SDA
SDA
SDA
_______________________________________________________________________________________
SCL
SCL
SCL
SCL
C Port Expander with 8 Open-Drain I/Os
V+
V+
V+
V+
2
C transmission (to any device, not neces-
GND
GND
GND
GND
AD0
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
V+
V+
V+
V+
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DEVICE ADDRESS
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 3).
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
I/O port inputs switch at the CMOS-logic levels as
determined by the expander’s supply voltage, and are
overvoltage tolerant to +6V, independent of the
expander’s supply voltage.
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed
through the serial interface. The state of the input ports
is stored in an internal “snapshot” register for transition
monitoring. The snapshot is continuously compared
with the actual input conditions, and if a change is
detected for any port, INT is asserted to signal a state
change. An internal transition flag is set for that port.
The input is sampled (internally latched into the snap-
shot register) and the old transition flags cleared during
the I
access. The previous port transition flags are read
through the serial interface as the second byte of a
2-byte read sequence.
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
C acknowledge of every MAX7321 read and write
—
—
—
—
I7
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
I/O Port Input Transition Detection
—
—
—
—
I6
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
40kΩ INPUT PULLUP ENABLES
—
—
—
—
I5
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
I4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
I3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
I2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Port Inputs
—
—
—
—
I1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
I0
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y