MAX7319ATE+ Maxim Integrated Products, MAX7319ATE+ Datasheet - Page 9

IC I/O EXPANDER I2C 8B 16TQFN-EP

MAX7319ATE+

Manufacturer Part Number
MAX7319ATE+
Description
IC I/O EXPANDER I2C 8B 16TQFN-EP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX7319ATE+

Interface
I²C
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 1. 2-Wire Serial-Interface Timing Details
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7319’s 7-bit slave
address plus R/W bit, then 1 or more data bytes, and
finally a STOP condition (Figure 2).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
The acknowledge bit is a clocked 9th bit the recipient
uses to acknowledge receipt of each byte of data
(Figure 4). Each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the
high period of the clock pulse. When the master is
transmitting to the MAX7319, the MAX7319 generates
the acknowledge bit because the device is the recipient.
SDA
SCL
t
HD,STA
START CONDITION
_______________________________________________________________________________________
I
2
C Port Expander with Eight Inputs and
START and STOP Conditions
t
LOW
t
R
t
SU,DAT
t
HIGH
t
F
Acknowledge
Maskable Transition Detection
Bit Transfer
t
HD,DAT
t
REPEATED START CONDITION
SU,STA
Figure 3. Bit Transfer
When the MAX7319 is transmitting to the master, the
master generates the acknowledge bit because the
master is the recipient.
Figure 2. START and STOP Conditions
Figure 4. Acknowledge
SDA
SCL
SDA
SCL
TRANSMITTER
CONDITION
RECEIVER
SDA BY
SDA BY
START
S
SCL
t
HD,STA
CONDITION
DATA LINE STABLE;
START
DATA VALID
S
1
CHANGE OF DATA
ALLOWED
t
SU,STO
2
FOR ACKNOWLEDGMENT
CONDITION
STOP
CLOCK PULSE
t
BUF
8
CONDITION
START
CONDITION
9
STOP
P
9

Related parts for MAX7319ATE+