Z0220112VSGR3470 Zilog, Z0220112VSGR3470 Datasheet - Page 25
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Z0220112VSGR3470
Manufacturer Part Number
Z0220112VSGR3470
Description
IC MODEM 2400BPS DSP AFE 44-PLCC
Manufacturer
Zilog
Specifications of Z0220112VSGR3470
Data Format
V.21, V.22, V.23, Bell 103, Bell 212A
Baud Rates
2.4k
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PS000904-0107
Host Port Interface
Eye Pattern Interface
Table 12. Synchronous Serial Interface Port
The host parallel port interface consists of 15 signal pins: 8-bit bidirectional data
bus pins (HD7–HD0), 3-bit Address bus (HA2–HA0), four control lines, which
include the HoST READ (HRD), HOST WRITE (HWR), HOST CHIP SELECt (HCS), and
HOST INTERRUPT REQUEST (HIRQ). Multiple interrupt sources are provided in the
Z02201, each of which can be masked under host control.
The host parallel interface allows the host to access the data pump RAM address
and data bits, transmit and receive data, control the RAM and status bits, and read
data pump status bits. The host can access eye pattern functions, transmit and
receive tones, and access adaptive equalizer coefficients in modem-type
applications.
The host parallel interface is compatible with standard 8-bit microprocessors,
which include the Z8 and Z80 bus.
The eye pattern interface consists of three pins: EYE PATTERN DATA (EYEOUT),
EYE PATTERN CLOCK (EYECLK), and EYE PATTERN STROBE (EYESTB). Sixteen
bits of data are serially transmitted via EYEOUT, under control of EYESTB and EYE-
CLK. The first byte is the X-coordinate and the second byte is Y-coordinate of the
sample. The least significant bit is presented first for both the X and Y coordi-
nates. A schematic of an eye pattern circuit is found in
specification.
The EYE PATTERN DATA, EYEOUT, outputs a serial bit stream containing data for
display of the eye pattern on an oscilloscope after D/A conversion. 8 bits of the X-
axis data and 8 bits of the Y-axis are output as a single 16-bit data stream with the
Pin
TxD
RxD
RTS
RLSD
TCLK
RCLK
Signal Name
Transmit Data
Receive Data
Request To Send
Receive Line Signal Detect
Transmit Data Clock
Receive Data Clock
V.22BIS Data Pump with Integrated AFE
Figure 16
at the end of this
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