AD9995KCPZRL Analog Devices Inc, AD9995KCPZRL Datasheet - Page 7

• Manufacturer Part Number: AD9995KCPZRL
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9995KCPZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore,
every code must have a finite width. No missing codes guaran-
teed to 12-bit resolution indicates that all 4096 codes must be
present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to
the peak deviation of the output of the AD9995 from a true
straight line. The point used as zero scale occurs 0.5 LSB
before the first code transition. Positive full scale is defined as
a level 1.5 LSB beyond the last code transition. The deviation
is measured from the middle of each particular output code to
the true straight line. The error is then expressed as a percent-
EQUIVALENT CIRCUITS
REV. 0
THREE-
STATE
DATA
Circuit 2. Digital Data Outputs
AVDD
AVSS
Circuit 1. CCDIN
R
DVDD
DVSS
AVSS
DRVDD
DRVSS
DOUT
–7–
RG, H1–H4
ENABLE
age of the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated in
LSB and represents the rms noise level of the total signal chain at
the specified gain setting. The output noise can be converted to
an equivalent voltage using the relationship 1 LSB = (ADC Full
Scale/2
AD9995, 1 LSB is 0.488 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
n
codes), where n is the bit resolution of the ADC. For the
Circuit 4. H1–H4, RG Drivers
Circuit 3. Digital Inputs
DVDD
DVSS
HVDD OR
RGVDD
HVSS OR
RGVSS
AD9995
OUTPUT