AD9805JS Analog Devices Inc, AD9805JS Datasheet - Page 12

• Manufacturer Part Number: AD9805JS
• Description: IC CCD SIGNAL PROC 10BIT 64-PQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9805JS

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: Microprocessor
• Current - Supply: 86mA
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Color Pointer
Both the AD9807 and the AD9805 use Bits 6 and 7 in the
Configuration Register to direct data to the corresponding
internal registers. Table III shows the mapping of Bits 6 and 7
to their corresponding color.
Configuration Register 2
Configuration Register 2 controls several functions: color/black
and white selection, CDS enabling, A/D Reference Control
and Input Clamp Mode. Figure 7 shows the AD9807 and
AD9805 Configuration Register 2 format. Setting Bit 0 enables
the three internal CDS blocks of the AD9807/AD9805. Reset-
ting Bit 0 disables the internal CDS blocks, configuring the part
for SHA operation. Setting Bit 1 places the AD9807/AD9805 in
single-channel (black & white) mode. In this mode, only one of
the three input channels is used. The color bits in the configu-
ration register at the time of the last write indicate the particular
channel used. Resetting Bit 1 places the AD9807/AD9805 in
color mode and all three input channels are enabled. Bits 2-4
control the full-scale input span of the A/D. Setting Bit 2 results in
a 4 V p-p input span. Setting Bit 3 results in a 2 V p-p full-scale
input span. Setting Bit 4 results in a full-scale span set by an
external reference connected to the VREF pin of the AD9807/
AD9805 (Full Scale = 2 VREF). Resetting Bits 2, 3 or 4
disables that particular mode. Bits 6 and 7 select the desired
clamp mode (see Figure 17). Table IV shows the truth table
for clamp mode functionality. Line clamp mode allows control
of the input switch (S1) via CDSCLK1 only while STRTLN is
reset. Pixel clamp mode allows control of the input switch (S1)
via CDSCLK1 regardless of the state of STRTLN. No clamp
mode disables the input switch (S1) regardless of the selected
mode of CDS operation.
Figure 7. AD9807/AD9805 Configuration Register 2 Format
AD9807/AD9805
Bit 7
0
0
1
1
Bit 7
0
0
1
1
7
6
Table IV. Clamp Mode Truth Table
Table III. Color Pointer Map
5
4
3
Bit 6
0
1
0
1
Bit 6
0
1
0
1
2
1
0
Color Register
Red
Green
Blue
RESERVED
CDSEN
BLACK & WHITE
ADC FULL SCALE = 4V
ADC FULL SCALE = 2V
EXTERNAL REFERENCE
SET TO 0
CLAMP MODE SELECT
CLAMP MODE SELECT
Clamp Mode
Line Clamp
Pixel Clamp
No Clamp
RESERVED
–12–
Input Offset Registers
The Input Offset Registers control the amount of analog offset
applied to the analog inputs prior to the PGA portion of the
AD9807/AD9805; there is one Input Offset Register for each
color. Figure 8 shows the Input Offset Register format. The
offset range may be varied between –80 mV and 20 mV. The
data format for the Input Offset Registers is straight binary
coding. An all “zeros” data word corresponds to –80 mV. An
all “ones” data word corresponds to 20 mV. The offset is
variable in 256 steps. The contents of the color pointer in the
Configuration Register at the time an Input Offset Register is
written indicates the color for which that offset setting applies.
PGA Gain Registers
Bits 0–3 of the PGA Gain Registers control the amount of gain
applied to the analog inputs prior to the A/D conversion
portion of the AD9807/AD9805; there is one PGA Gain
Register for each channel. Figure 9 shows the PGA Gain Register
format. The gain range may be varied between 1 and 4. The
data format for the PGA Gain Registers is straight binary
coding. An all “zeros” data word corresponds to an analog
gain of 1. An all “ones” data word corresponds to an analog
gain of 4. The gain is variable in 16 steps (see Figure 16).
The contents of the color pointer in the Configuration
Register at the time a PGA Gain Register is written indicates
the color for which that gain setting applies. Bits 4–7 of the PGA
Gain Registers are reserved.
Odd, Even Offset Registers
The Odd and Even Offset Registers provide a means of digitally
compensating the odd and even offset error (Register Imbal-
ance) typical of multiplexed CCD imagers; there is one Odd
and one Even Offset Register for each color. Figure 10 shows
the AD9807/AD9805 Odd and Even Offset Register Formats.
The data format for the Odd and Even Offset Registers is twos
complement. The offsets may be varied between positive
7
Figure 8. Input Offset Registers Format
Figure 9. PGA Gain Registers Format
6
7
5
6
4
5
3
4
2
3
1
2
0
1
0
ANALOG OFFSET (LSB)
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET (MSB)
PGA0
PGA1
PGA2
PGA3
RESERVED
RESERVED
RESERVED
RESERVED
REV. 0