AD9895KBCRL Analog Devices Inc, AD9895KBCRL Datasheet - Page 6

• Manufacturer Part Number: AD9895KBCRL
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9895KBCRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9891/AD9895
TIMING SPECIFICATIONS
Parameter
MASTER CLOCK, CLI (Figure 7)
AFE CLAMP PULSES
AFE SAMPLE LOCATION
DATA OUTPUTS (Figure 12)
SERIAL INTERFACE (Figures 52 and 53)
NOTES
1
2
ABSOLUTE MAXIMUM RATINGS
Parameter
AVDD1, AVDD2
TCVDD
HVDD
RGVDD
DVDD
DRVDD
RG Output
H1–H4 Output
Digital Outputs
Digital Inputs
SCK, SL, SDATA
VRT, VRB
BYP1–BYP3, CCDIN
Junction Temperature
Lead Temperature, 10 sec
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9891 and AD9895 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Parameter is programmable.
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
CLI Clock Period, AD9891
CLI High/Low Pulsewidth, AD9891
CLI Clock Period, AD9895
CLI High/Low Pulsewidth, AD9895
Delay from CLI Rising Edge to Internal Pixel Position 0
CLPDM Pulsewidth
CLPOB Pulsewidth
SHP Sample Edge to SHD Sample Edge, AD9891
SHP Sample Edge to SHD Sample Edge, AD9895
Output Delay from DCLK Rising Edge
Pipeline Delay from SHP/SHD Sampling
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
2
1
(Figure 13)
With
Respect
To
AVSS
TCVSS
HVSS
RGVSS
DVSS
DRVSS
RGVSS
HVSS
DVSS
DVSS
DVSS
AVSS
AVSS
1
(Figure 10)
Min Max
–0.3 +3.9
–0.3 +3.9
–0.3 +5.5
–0.3 +5.5
–0.3 +3.9
–0.3 +3.9
–0.3 RGVDD + 0.3
–0.3 HVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
(C
otherwise noted.)
L
1
= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
150
350
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
Symbol
t
t
t
t
t
t
f
t
t
t
t
t
CONV
CONV
CLIDLY
S1
S1
OD
SCLK
LS
LH
DS
DH
DV
–6–
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
Model
AD9891KBC –20°C to +85°C
AD9895KBC –20°C to +85°C
JA
JC
= 61°C/W
= 29.7°C/W
Min
50
20
33.3
13
4
2
20
13
10
10
10
10
10
10
CLI
= 20 MHz [AD9891] or 30 MHz [AD9895], unless
Temperature
Range
ORDERING GUIDE
Typ
16.7
6
10
20
25
16.7
8
25
9
Max
WARNING!
Package
Description
CSPBGA
CSPBGA
ESD SENSITIVE DEVICE
Unit
ns
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
Package
Option
BC-64
BC-64
REV. A