MAX9223ETI+ Maxim Integrated Products, MAX9223ETI+ Datasheet - Page 10

• Manufacturer Part Number: MAX9223ETI+
• Description: IC SERIALIZER LP 28-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX9223ETI+

• Function: Serializer/Deserializer
• Data Rate: 220Mbps
• Input Type: Parallel
• Output Type: Parallel
• Number Of Inputs: 22
• Number Of Outputs: 1
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The parallel data input of the MAX9223 serializer is
latched on the rising edge of PCLKIN. Figure 3 shows
the serializer input timing.
The serial-data output of the MAX9224 deserializer is
valid on the rising edge of PCLKOUT. Figure 4 shows
the deserializer output timing.
Driving PWRDN low puts the MAX9223 in power-down
mode and sends a pulse to power down the MAX9224. In
power-down mode, the DLL is stopped, SDO+/SDO- are
high impedance to ground and differential, and the LCDS
link is weakly biased around V
and all inputs low, the combined MAX9223/MAX9224
supply current is reduced to 3.5µA or less.
Driving PWRDN high starts DLL lock to PCLKIN and ini-
tiates a MAX9224 power-up sequence. The MAX9223
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Figure 5. Multilevel LCDS Output Representation
10
______________________________________________________________________________________
G*
LCDS SERIAL DATA OUTPUT FOR EXAMPLE INPUT (SD0±)
NOTE: THERE IS NO TRANSITION BETWEEN OH BITS.
1
Applications Information
Power-Down and Power-Up
1
PCLK IN
DIN[21:0]
PARALLEL DATA INPUT
INPUT
DIN
EXAMPLE
0
PCLKIN Latch Edge
DD
PCLKOUT Strobe
- 0.8V. With PWRDN
1
1
0
1
1
*INTERNALLY PREPENDED BIT—ALWAYS 0.
0
2
1
1
3
0
9
1
10
0
0
LCDS output is not driven until the DLL locks. 4096
clock cycles are required for the power-up and link
synchronization, before valid DIN can be latched. See
Figure 6 for an overall power-up and power-down tim-
ing diagram. For normal operation, PCLKIN must be
running and settled before driving PWRDN high.
If V
ground and differential.
The MAX9223/MAX9224 are designed to function nor-
mally in the event of a slight shift in ground potential.
However, the MAX9224 deserializer ground must be
within ±0.2V relative to the MAX9223 serializer ground
to maintain proper operation.
The MAX9224 parallel outputs are powered from V
which accepts a +1.71V to +3.465V supply, allowing
direct interface to inputs with 1.8V to 3.3V logic levels.
11
0
DD
12
1
1
MAX9224 Output Buffer Supply (V
= 0, the LCDS outputs are high impedance to
13
0
14
0
1
1
20
1
21
1
Ground-Shift Tolerance
1
1
OH
OH
DDO
DDO
)
,