MAX9257GTL+ Maxim Integrated Products, MAX9257GTL+ Datasheet - Page 39

• Manufacturer Part Number: MAX9257GTL+
• Description: IC SER/DESER PROG 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX9257GTL+

• Function: Serializer/Deserializer
• Data Rate: 840Mbps
• Input Type: Serial
• Output Type: LVDS
• Number Of Inputs: 16
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the LVDS driver termination resistor (R
AC-coupling capacitors (C). The RC time constant for
four equal-value series capacitors is (C x (R
R
impedance (usually 100Ω). This leaves the capacitor
selection to change the system time constant. In the fol-
lowing example, the capacitor value for a droop of 2% is
calculated:
where:
C = AC-coupling capacitor (F)
t
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
R
R
The bit time (t
of the pixel clock divided by the total number of bits.
The maximum DSV for the MAX9257 encoding equals
to the total number of bits transmitted in one pixel clock
cycle. This means that t
The capacitor for 2% maximum droop at 16MHz paral-
lel rate clock is:
Total number of bits is = 10 (data) + 2 (HSYNC and
VSYNC) + 2 (encoding) + 2 (parity) = 16
C ≥ 0.062µF
Jitter due to droop is proportional to the droop and tran-
sition time:
t
where:
t
t
D = droop (% of signal amplitude)
B
J
J
TT
TD
TD
TR
= t
= jitter(s)
= bit time(s)
= transition time(s) (0 to 100%)
= driver termination resistor (Ω)
= receiver termination resistor (Ω)
and R
TT
x D
TR
C
Fully Programmable Serializer/Deserializer
are required to match the transmission line
C
C
B
=
) is the serial-clock period or the period
= −
-
=
ln(
-
______________________________________________________________________________________
ln(
ln(
1
1
-
1
4
.
-
-
02
B
4
4
×
D
D
x DSV ≤ t
×
×
) (
) (
3 91
) (
×
t
×
t
.
×
B
B
100
×
R
R
×
ns
TR
DSV
TR
DSV
Ω
×
+
+
T
16
+
.
R
R
100
TD
TD
TD
), and the series
)
)
Ω
with UART/I
)
TD
+ R
TR
))/4.
Jitter due to 2% droop and assumed 1ns transition time is:
t
t
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter. Use
high-frequency, surface-mount ceramic capacitors.
All single-ended inputs and outputs on the MAX9257
are powered from V
the MAX9258 are powered from V
V
ply. The input levels or output levels scale with these
supply rails.
Separate the LVCMOS/LVTTL signals and LVDS signals
to prevent crosstalk. A four-layer PCB with separate lay-
ers for power, ground, LVDS, and digital signals is rec-
ommended. Layout PCB traces for 100Ω differential
characteristic impedance. The trace dimensions
depend on the type of trace used (microstrip or
stripline). Note that two 50Ω PCB traces do not have
100Ω differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
Route the PCB traces for an LVDS channel (there are
two conductors per LVDS channel) in parallel to main-
tain the differential characteristic impedance. Place the
100Ω (typ) termination resistor at both ends of the
LVDS driver and receiver. Avoid vias. If vias must be
used, use only one pair per LVDS channel and place
the via for each line at the same point along the length
of the PCB traces. This way, any reflections occur at
the same time. Do not make vias into test points for
ATE. Make the PCB traces that make up a differential
pair the same length to avoid skew within the differen-
tial pair.
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables offer superior signal quality compared to ribbon
cable and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise
as common mode that is rejected by the LVDS receiver.
J
J
CCOUT
= 1ns x 0.02
= 20ps
Power-Supply Circuits and Bypassing
2
can be connected to a +1.71V to +3.6V sup-
C Control Channel
CCIO
. All single-ended outputs on
Cables and Connectors
CCOUT
Board Layout
. V
CCIO
and
39