MAX9249GCM/V+T Maxim Integrated Products, MAX9249GCM/V+T Datasheet - Page 18

• Manufacturer Part Number: MAX9249GCM/V+T
• Description: IC SERIALIZER GMSL LVDS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9249GCM/V+T

• Function: Serializer
• Data Rate: 2.5Gbs
• Input Type: LVDS
• Output Type: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Outputs: -
• Number Of Inputs: -

Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Figure 14. VESA Standard Panel Clock and Bit Assignment
the embedded serial clock and then samples, decodes,
and descrambles before outputting the data. Figures
15 and 16 show the serial-data packet format before
scrambling and 8B/10B coding. In 3-channel or 4-chan-
nel mode, 21 or 28 bits come from the RXIN_ _ LVDS
inputs. Control bits can be mapped to DIN27 and DIN28
in 4-channel mode. The audio channel bit (ACB) con-
tains an encoded audio signal derived from the three I
inputs (SD/CNTL0, SCK, and WS). The forward control-
channel (FCC) bit carries the forward control data. The
last bit (PCB) is the parity bit of the previous 23 or 31 bits.
Figure 15. 3-Channel Mode Serial Link Data Format
18
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
DIN0
R0
_____________________________________________________________________________________
SET ACCORDING TO VESA STANDARD PANEL BITMAP.
DIN1
R1
(3 CHANNELS)
LVDS
DATA
DIN17 DIN18 DIN19 DIN20
RXIN0+/RXIN0-
RXIN1+/RXIN1-
RXIN2+/RXIN2-
RXIN3+/RXIN3-
B5
RXCLKIN+
RXCLKIN-
24 BITS
HS
VS
DE
CHANNEL BIT
CYCLE N-1
R1
G2
B3
R7
AUDIO
ACB
CHANNEL BIT
CONTROL-
FORWARD
FCC
R0
G1
B2
R6
CHECK BIT
PACKET
PARITY
PCB
RES
G0
DE
B1
2
S
R5
B0
VS
B7
In 4-channel mode, the MAX9249 serializes all bits of all
four lanes including RES by default. Set DISRES (D4 of
Register 0x0D) to 1 to map CNTL1 to DIN27 instead of
RES.
The MAX9249 uses the reverse control channel to
receive I
deserializer in the opposite direction of the video stream.
The reverse control channel and forward video data
coexist on the same twisted pair forming a bidirectional
link. The reverse control channel operates independently
from the forward control channel. The reverse control
channel is available 500Fs after power-up. The MAX9249
temporarily disables the reverse control channel for
350Fs after starting/stopping the forward serial link.
The MAX9249 uses the DRS input to set the RXCLKIN_
frequency. Set DRS high for an RXCLKIN_ frequency of
6.25MHz to 12.5MHz (4-channel mode) or 8.33MHz to
16.66MHz (3-channel mode). Set DRS low for normal
operation with an RXCLKIN_ frequency of 12.5MHz
to 78MHz (4-channel mode) or 16.66MHz to 104MHz
(3-channel mode).
HS
R4
G5
B6
CYCLE N
2
C/UART and interrupt signals from the GMSL
G4
G7
R3
B5
G3
G6
R2
B4
R1
G2
B3
R7
Reverse Control Channel
R0
G1
B2
R6
Data-Rate Selection
Reserved Bit (RES)