DS92001TMAX/NOPB National Semiconductor, DS92001TMAX/NOPB Datasheet - Page 9

• Manufacturer Part Number: DS92001TMAX/NOPB
• Description: IC BLVDS-BLVDS BUFFER 3.3V 8SOIC
• Manufacturer: National Semiconductor
• Type: Bufferr

Specifications of DS92001TMAX/NOPB

• Tx/rx Type: LVDS
• Delay Time: 2.0ns
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 65mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Elements: 1
• Number Of Receivers: 1
• Number Of Drivers: 1
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Diff. Input Low Threshold Volt: -70mV
• Differential Output Voltage: 500mV
• Transmission Data Rate: 400Mbps
• Propagation Delay Time: 2ns
• Power Dissipation: 726mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Capacitance - Input: -
• Lead Free Status / Rohs Status: Compliant
• Other names: DS92001TMAX

Application Information
The DS92001 can be used as a "stub-hider." In many sys-
tems, signals are distributed across backplanes, and one of
the limiting factors for system speed is the "stub length" or the
distance between the transmission line and the unterminated
receivers on the individual cards. See Figure 8. Although it is
generally recognized that this distance should be as short as
possible to maximize system performance, real-world pack-
aging concerns and PCB designs often make it difficult to
make the stubs as short as the designer would like. The
DS92001, available in the LLP (Leadless Leadframe Pack-
age) package, can improve system performance by allowing
the receiver to be placed very close to the main transmission
line either on the backplane itself or very close to the con-
nector on the card. Longer traces to the LVDS receiver may
be placed after the DS92001. This very small LLP package is
a 75% space savings over the SOIC package.
The DS92001 may also be used as a repeater as shown in
Figure 9. The signal is recovered and redriven at full strength
down the following segment. The DS92001 may also be used
as a level translator, as it accepts LVDS, BLVDS, and
LVPECL inputs.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high fre-
quency ceramic (surface mount is recommended) 0.1μF and
0.01μF capacitors in parallel at the power supply pin with the
smallest value capacitor closest to the device supply pin. Ad-
ditional scattered capacitors over the printed circuit board will
improve decoupling. Multiple vias should be used to connect
the decoupling capacitors to the power planes. A 10μF (35V)
or greater solid tantalum capacitor should be connected at the
power entry point on the printed circuit board between the
supply and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB board layers (top to bottom): LVDS sig-
nals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
For PC board considerations for the LLP package, please re-
fer to application note AN-1187 “Leadless Leadframe Pack-
age.” It is important to note that to optimize signal integrity
(minimize jitter and noise coupling), the LLP thermal land pad,
which is a metal (normally copper) rectangular region located
under the package as seen in Figure 10, should be attached
to ground and match the dimensions of the exposed pad on
the PCB (1:1 ratio).
9
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential
impedance of your transmission medium (ie. cable) and ter-
mination resistor. Run the differential pair trace lines as close
together as possible as soon as they leave the IC (stubs
should be < 10mm long). This will help eliminate reflections
and ensure noise is coupled as common-mode. In fact, we
have seen that differential signals which are 1mm apart radi-
ate far less noise than traces 3mm apart since magnetic field
cancellation is much better with the closer traces. In addition,
noise induced on the differential lines is much more likely to
appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase difference
between signals which destroys the magnetic field cancella-
tion benefits of differential signals and EMI will result. Do not
rely solely on the auto-route function for differential traces.
Carefully review dimensions to match differential impedance
and provide isolation for the differential lines. Minimize the
number of vias and other discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use
arcs or 45° bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
TERMINATION
Use a termination resistor which best matches the differential
impedance or your transmission line. The resistor should be
between 90Ω and 130Ω for point-to-point links. Multidrop
(driver in the middle) or multipoint configurations are typically
terminated at both ends. The termination value may be lower
than 100Ω due to loading effects and in the 50Ω to 100Ω
range. Remember that the current mode outputs need the
termination resistor to generate the differential voltage.
Surface mount 1% - 2% resistors are the best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be < 10mm
(12mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance
(< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.
Improper probing will give deceiving results.
FIGURE 10. LLP Thermal Land Pad and Pin Pads - Top
View
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