DS2175 Maxim Integrated Products, DS2175 Datasheet
DS2175
Specifications of DS2175
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DS2175 Summary of contents
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... C available, designated DS2175N DESCRIPTION The DS2175 is a low–power CMOS elastic–store memory optimized for use in primary rate telecommu- nications transmission equipment. The device serves as a synchronizing element between async data streams and is compatible with North American (T1–1.544 MHz) and European (CEPT–2.048 MHz) rate networks ...
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... DS2175 BLOCK DIAGRAM Figure DS2175 ...
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... DD PCM BUFFER The DS2175 utilizes a 2–frame buffer to synchronize in-coming PCM data to the system backplane clock. Buffer depth is mode–dependent; 2.048 MHz to 2.048 MHz applications utilize 64 bytes of buffer memory, while all other modes are supported by 48 bytes. The buffer samples data at RSER on the falling edge of RCLK. Output data appears at SSER and is updated on the rising edge of SYSCLK. The buffer depth is constantly monitored by onboard contention logic ...
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... No F–bit position exists in 2.048 MHz system side applications. PARALLEL COMPATIBILITY The DS2175 is compatible with parallel and serial backplanes. Channel 1 data appears at SSER after a rising edge at SFSYNC (serial applications 1). The device utilizes a look–ahead circuit in parallel applications ( 0), and presents data 8 clocks early as shown in Figures 4 and 5. Converting SSER to a parallel format requires an HC595 shift register ...
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... In 1.544 MHz receive side applications (RCLKSEL=0), the F–bit position contains F–bit data extracted from the data stream at RSER. The F–bit position is forced to “1” in 2.048 MHz receive side applications (RCLKSEL=1 2.048 MHz receive side applications (RCLKSEL=1), the E–bit position is forced to “1” and data in channels >24 is ignored DS2175 ...
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... This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. –1.0V to +7. – +125 C 260 C for 10 seconds DS2175 ...
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... All outputs except SLIP , which is open collector 4. All outputs MIN TYP 4.5 DD MIN TYP OUT MIN TYP - (0°C TO 70°C) MAX UNITS NOTES V +0 +0 =25°C) A MAX UNITS NOTES (0°C TO 70°C; V =5V±10%) DD MAX UNITS NOTES 16 mA +1.0 µ DS2175 1 ...
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... Output load capacitance = 100 pF. SYMBOL MIN TYP t 200 RCLK 100 RWH, t RWL t 100 SWH, t SWL t 200 SYSCLK PVD t PSS 500 SR –0.8V, and 10 ns maximum rise and fall times (0°C TO 70°C; V =5V±10%) DD MAX UNITS NOTES RWH SWH 100 ns ns DS2175 ...
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... RECEIVE AC TIMING DIAGRAM Figure 6 SYSTEM AC TIMING DIAGRAM Figure DS2175 ...
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... DS2175 T1/CEPT ELASTIC STORE PKG DIM A IN. B IN. C IN. D IN. E IN. F IN. G IN. H IN. J IN DS2175 16-PIN MIN MAX 0.740 0.780 0.240 0.260 0.120 0.140 0.300 0.325 0.015 0.040 0.120 0.140 0.090 0.110 0.290 0.420 0.008 0.012 0.015 0.021 ...
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... DS2175S T1/CEPT ELASTIC STORE PKG DIM A IN. B IN. C IN. E IN. F IN. G IN. H IN. J IN. K IN DS2175 16-PIN MIN MAX 0.402 0.412 0.290 0.300 0.089 0.095 0.004 0.012 0.094 0.105 0.050 BSC 0.398 0.416 0.009 0.013 0.013 0.019 0.016 0.040 ...
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... DATA SHEET REVISION SUMMARY The following represent the key differences between 04/19/95 and 06/13/97 version of the DS2175 data sheet. Please review this summary carefully. 1. SYNC/CLOCK Relationship in timing diagram DS2175 ...