LTC1755EGN#PBF Linear Technology, LTC1755EGN#PBF Datasheet - Page 13

• Manufacturer Part Number: LTC1755EGN#PBF
• Description: IC SMART CARD INTERFACE 24SSOP
• Manufacturer: Linear Technology

Specifications of LTC1755EGN#PBF

• Applications: Smart Card
• Voltage - Supply: 2.7 V ~ 6 V
• Package / Case: 24-SSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -

APPLICATIO S I FOR ATIO
I
Some smart cards still require I
format it is permissible to impose an L before the signal
line has returned H. This is used, for example, as an
acknowledge signal. Such a scenario will cause a collision
as shown in Figure 3.
Figure 4 shows an analog level translation technique that
can be used along with the LTC1755 to support I
cards. In this technique it is important to connect the gate
of the external MOSFET to the lower of the two supplies
(i.e., the lower of V
a fixed 5V supply, the gate of MN1 should be connected to
V
gate of MN1 should be connected to DV
case, the gate may need to be connected to a digital signal
ranging from 0V to DV
the LTC1755 is in shutdown. Otherwise, the the LTC1755
will try to assert an L on the microcontroller side of the
channel when it is in shutdown.
Supporting Synchronous and Asyncronous Cards
In synchronous/asynchronous applications it is neces-
sary to switch the CLK pin of the card socket from a free
running asynchronous clock to a controlled syncronous
clock. To avoid glitches and pulses shorter than the
minimum allowed pulse width, the circuit shown in Figure
5 should be used as a clock selection circuit. Note that for
this circuit to be effective the SYNC input should be held
constant while switching the ASYNC\SYNC control signal.
Low Power Operation
The LTC1755/LTC1756 are inherently low power devices.
When there is no Smart Card present the supply current is
2
CC
C
TM
. If DV
Compatibility
DATA
I/O
CC
is operating from a regulated 3.3V supply, the
TRANSMIT
CC
NORMAL
U
or DV
CC
so that it can be disabled when
U
CC
). If DV
2
C compatibility. In the I
W
NORMAL
RECEIVE
Figure 3. Possible Bidirectional Channel Scenarios
CC
is operating from
CC
. In the latter
U
2
C smart
TRANSMIT MODE (COLLISION)
2
C
I/O PULLED LOW DURING
I
less than 10 A. If DV
When a Smart Card is present the LTC1755/LTC1756
operate with a quiescent current of only 60 A, thus the
majority of power is consumed by charge pump losses
and the card itself. If the card can be made to consume less
power during idle times a significant power savings will be
achieved. Whenever possible Clock Stop Mode should be
used (or alternatively a very low “idling” clock speed).
Furthermore, in the Active state, the bidirectional pins
should all be relinquished whenever possible since there
is some static current flow when a bidirectional pin is
pulled down.
ASYNC IN
2
SYNC IN
C is a trademark of Philips Electronics N.V.
MICROCONTROLLER
ASYNC SYNC
Figure 5. Glitchless Clock Selection Circuit
POWER
Figure 4. I
DATA
TO
5V
D
*CONNECT GATE TO V
CONNECT GATE TO DV
FOR DV
Q
Q
20k
R1
2
C Level Translation Technique
CC
CC
TN2460T (TEMIC/SILICONIX)
is 0V the current drops below 1 A.
LTC1755/LTC1756
2N7002T1 (MOTOROLA)
3.3V APPLICATONS
D
MN1
RECEIVE MODE (COLLISION)
DATA PULLED LOW DURING
DV
Q
Q
LTC1755
CC
CC
CC
FOR DV
*
OR DV
V
I/O
CC
CC
CC
= 5V APPLICATIONS
LOGIC LEVEL SIGNAL
17556 F05
17556 F04
TO
SMART CARD
17556 F03
13
TO C
IN