CYWB0224ABM-BVXI Cypress Semiconductor Corp, CYWB0224ABM-BVXI Datasheet - Page 2

• Manufacturer Part Number: CYWB0224ABM-BVXI
• Description: IC WEST BRIDGE HS-USB 100VFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWB0224ABM-BVXI

• Controller Type: Peripheral
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Current - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-VFBGA
• Applications: Multimedia
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Overview
The SLIM™ Architecture
The Simultaneous Link to Independent Multimedia (SLIM) archi-
tecture allows three different interfaces (P-port, S-port and
U-port) to connect to one another independently.
With this architecture, connecting a device using Astoria to a PC
through USB does not disturb any of the functions of the device.
The device can still access mass storage at the same time the
PC is synchronizing with the main processor.
The SLIM architecture enables new usage models in which a PC
can access a mass storage device independent of the main
processor, or enumerate access to both the mass storage and
the main processor at the same time.
In a handset, this typically enables using the phone as a thumb
drive, downloading media files to the phone while still having full
functionality available on the phone, or using the same phone as
a modem to connect the PC to the web.
8051 Microprocessor
The 8051 microprocessor embedded in Astoria does basic trans-
action management for all the transactions between P-Port,
S-Port, and U-Port. The 8051 does not reside in the data path; it
manages the path. The data path is optimized for performance.
The 8051 executes firmware that supports NAND, SD, SDIO,
MMC+, and CE-ATA devices at the S-Port. For the NAND device,
the 8051 firmware follows the smart media algorithm to support:
•
•
•
•
Configuration and Status Registers
The West Bridge Astoria device includes configuration and
status registers that are accessible as memory mapped registers
through the processor interface. The configuration registers
allow the system to specify certain behavior of Astoria. For
example, it is able to mask certain status registers from raising
an interrupt. The status registers convey various status, such as
the addresses of buffers for read operations.
Processor Interface (P-Port)
Communication with the external processor is realized through a
dedicated processor interface. This interface is configured to
support different interface standards. This interface supports
multiplexing and nonmultiplexing address or data bus in both
synchronous and asynchronous pseudo CRAM-mapped, and
nonmultiplexing address or data asynchronous SRAM-mapped
memory accesses. The interface also can be configured to a
pseudo NAND interface to support the processor’s NAND
interface. In addition, this interface can be configured to support
SPI slave. Asynchronous accesses can reach a bandwidth of up
Physical to logical management
Four random bits ECC detection and correction support
Wear leveling
NAND Flash bad blocks handling
CONFIDENTIAL
PRELIMINARY
to 66.7 MBps. Synchronous accesses can be performed at 33
MHz across 16 bits for up to 66.7 MBps bandwidth.
The memory address is decoded to access any of the multiple
endpoint buffers inside Astoria. These endpoints serve as buffers
for data between each pair of ports, for example, between the
processor port and the USB port. The processor writes and reads
into these buffers via the memory interface.
Access to these buffers is controlled by either using a DMA
protocol or using an interrupt to the main processor. These two
modes are configurable by the external processor.
As a DMA slave, Astoria generates a DMA request signal to
signify to the main processor that a specific buffer is ready to be
read from or written to. The external processor monitors this
signal and polls Astoria for the specific buffers ready for read or
write. It then performs the appropriate read or write operations
on the buffer through the processor interface. This way, the
external processor only deals with the buffers to access a
multitude of storage devices connected to Astoria.
In the Interrupt mode, Astoria communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Astoria for the specific
buffers ready for read or write, and it performs the appropriate
read or write operations through the processor interface.
USB Interface (U-Port)
In accordance with the USB 2.0 specification, Astoria can
operate in Full Speed USB mode in addition to High Speed USB.
The USB interface consists of the USB transceiver. The USB
interface is accessible by both the P-Port and the S-Port.
The
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Astoria also has an integrated USB switch shown in
allows interfacing to an external Full Speed USB PHY.
Figure 1. U-Port With Switch and Control Block
Mass Storage Support (S-Port)
The S-Port is configurable in six different interface modes, either
simultaneously supporting an SD/SDIO/MMC+/CE-ATA port and
a 8-bit SLC or MLC NAND Flash ports, supporting two
SD/SDIO/MMC+/CE-ATA ports, supporting up to eight Chip
Enable (CE#) for 8-bit or 16-bit SLC or MLC NAND Flash port,
supporting SD/SDIO/MMC+/CE-ATA port and GPIO, supporting
NAND Flash port and GPIO, and GPIO. These configurations
are controlled by the 8051 firmware. The 16-bit NAND Flash
interface can only be used when there is no other mass storage
device connected to the S-Port.
USB 2.0
XCVR
Astoria
CYWB0224ABS, CYWB0224ABM
CYWB0226ABS, CYWB0226ABM
UVALID
USBALLO
USB
USB Switch
and Control
Block
interface
USB Port
supports
(U Port)
programmable
SWD+
SWD-
D+
D-
Figure 1
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