IXDP610PI IXYS, IXDP610PI Datasheet - Page 3

• Manufacturer Part Number: IXDP610PI
• Description: IC PWM CTRL BUS DIGITAL 18-PDIP
• Manufacturer: IXYS

Specifications of IXDP610PI

• Applications: PWM Motor Controller
• Interface: Microprocessor
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 18-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Operating Supply Voltage: - 0.3 V to + 5.5 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: -40 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sym. Pin Description
OUT2 10
OUT1 11 these two outputs provide the
Pin Description IXDP 610PI
3
ODIS 14 OUTPUT DISABLE - asserting
D0
D1
D2
D3
D4
D5
D6
D7
GND 9
V
CLK 13 CLOCK - the frequency of this
CC
12 POWER SUPPLY (5 V ± 10 %)
1
2
3
4
5
6
7
8
DATA BUS - the data bus on
the IXDP610 is configured for
input only. Data to be written to
the IXDP610 is placed on data
lines D0 through D7 during a
microprocessor write cycle.
Data is accepted by the
IXDP610 when CHIP SELECT
is low and the WRITE input
goes from a low to a high
state. The SELECT input
determines whether the data
written to the IXDP610 will go
to the Control latch or to the
Pulse Width latch. D0 is the
least significant bit and D7 is
the most significant bit.
CIRCUIT GROUND
COMPLEMENTARY OUTPUTS
complementary PWM signals.
The base period or cycle time
of these outputs is determined
by the CLOCK and the control
latch.
input determines the PWM
base frequency. CLK also
drives the internal state
machines. It has no effect on
any data bus transactions.
this Schmitt trigger input forces
the complementary outputs to
be immediately disabled
(OUT1 and OUT2 are forced
low). The complementary
outputs will remain low as long
as long as this input is asser-
ted, and for the duration of the
PWM cycle in which OUTPUT
DISABLE goes from low to
high; i.e., the complementary
outputs are not re-enabled
until the beginning of the next
PWM cycle, and then only if
OUTPUT DISABLE and the
Stop bit in the Control latch are
not asserted.
IXDP610PI
IXYS
SEL 15 SELECT-this input determines
RST 16 RESET-this asynchronous,
WR 17 WRITE-a low-to-high transition
CS
18 CHIP SELECT - this active low
whether data written into the
IXDP610 goes to the internal
Pulse Width (PW) latch or to
the Control latch. A zero on
this input (low voltage) directs
data to the PW latch; a one on
this input (high voltage) directs
data to the Control latch.
active low input disables the
outputs, chooses 8-bit count
mode in the PWM counter,
sets the clock to be "divided
by 1", clears Lock bit, and sets
the dead-time counter to 7.
Asserting RESET writes a
01000111 binary to the Control
latch. Asserting RESET is the
only way in which the Lock bit
in the control latch can be
cleared. Writes to the control
latch that occur after the lock
bit has been set to a one, can
only modify the Stop bit. Any
writes to the control latch,
while the RESET input is
asserted, are ignored. RESET
also clears the PW latch.
on this input, when CHIP
SELECT is low, causes data to
be written to the selected
IXDP610 latch. If SELECT is
low, the data is written to the
pulse width latch. If SELECT is
high, the data is written to the
control latch.
input enables the WRITE input
so that data may be written
into the IXDP610 latch
selected by the SELECT input.
Nomenclature of
Digital PWM Controller
IXDP 610 P I
IX
DP 610
© 2001 IXYS/DEI All rights reserved
P
I
(Example)
IXYS
Digital PWM Controller
Package Type
18-Pin Plastic DIP
Temperature Range
Industrial
(-40 to 85°C)
IXDP 610