CS61577-IL1Z Cirrus Logic Inc, CS61577-IL1Z Datasheet - Page 5

• Manufacturer Part Number: CS61577-IL1Z
• Description: IC LINE INTERFACE T1/E1 28PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61577-IL1Z

• Package / Case: 28-PLCC
• Applications: Networking
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1711

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Notes: 25. Crystal must meet specifications described in Appendix A.
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Crystal Frequency
TCLK Frequency
ACLKI Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
Crystal Frequency
TCLK Frequency
TCLK Duty Cycle for LEN2/1/0 = 0/0/0
ACLKI Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
26. ACLKI provided by an external source or TCLK.
27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
28. At max load of 1.6 mA and 50 pF.
29. Host Mode (CLKE = 1).
30. Extended Hardware Mode.
31. Hardware Mode, or Host Mode (CLKE = 0)
32. The transmitted pulse width does not depend on the TCLK duty cycle.
(Note 25)
(Note 26)
(Note 27) t
(Note 28)
(Note 28)
(Note 29)
(Note 30)
(Note 31)
(Note 29)
(Note 30)
(Note 31)
(Note 25)
(Note 32) t
(Note 26)
(Note 27) t
(Note 28)
(Note 28)
(Note 29)
(Note 30)
(Note 31)
(Note 29)
(Note 30)
(Note 31)
(TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
(TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
pwh1
pwh2
pwh1
f
f
t
t
t
t
t
t
t
t
f
f
aclki
aclki
t
t
t
t
t
t
t
t
su2
su1
su1
su1
su2
su1
su1
su1
tclk
tclk
f
h2
h1
h1
h1
f
h2
h1
h1
h1
t
t
t
t
c
c
r
f
r
f
/t
/t
/t
pw1
pw2
pw1
150
150
150
150
150
150
100
100
100
100
100
100
45
25
25
40
45
25
25
-
-
-
-
-
-
-
-
-
-
6.176000
8.192000
1.544
1.544
2.048
2.048
274
274
274
274
274
274
194
194
194
194
194
194
50
50
50
-
-
-
-
-
-
-
-
55
85
85
60
55
85
85
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%