IDT77010L155PQF IDT, Integrated Device Technology Inc, IDT77010L155PQF Datasheet - Page 3

• Manufacturer Part Number: IDT77010L155PQF
• Description: TRANSLATION DEVICE DPI 80-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77010L155PQF

• Applications: Data Interface
• Interface: DPI, UTOPIA
• Voltage - Supply: 3.3V, 5V
• Package / Case: 80-MQFP, 80-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77010L155PQF

Pin Definitions
Pin Definitions
Pin Definitions
Pin Definitions
SysClk
RST
LCRST
CONT_A
CONT_B
RxLED
TxLED
READ
WRITE
ALE
Add/Data0
Add/Data1
Add/Data2
Add/Data3
Add/Data4
Add/Data5
Add/Data6
Add/Data7
PHYCS
PHYINT
PHYRST
RCLK
RSOC
RENB
RCLAV
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
Signal Name
IDT77010
29
23
24
19
22
42
79
73
74
59
71
70
69
68
65
64
63
62
78
72
77
45
58
43
44
46
49
50
51
52
53
54
Number
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
O
O
O
O
O
O
I
O
O
I
O
I
I
I
I
I
I
I
I
Output
Input/
the RST signals from all line cards are connected together.
specific 77010 and PHY on a specific line card.
Output Control Pin A. This pin is controlled by a receive control cell. Default output = low.
Output Control Pin B. This pin is controlled by a receive control cell. Default output = low.
Active low. When low a receive cell is being transferred.
This pin may be used for receive activity LED.
Active low. When low a transmit cell is being transferred.
This pin may be used for transmit activity LED.
Utility bus read signal.
Utility bus write signal.
Utility bus address latch enable. Used for latching the address on the address phase of the Add/Data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus PHY chip select.
Utility bus PHY interrupt signal
Utility bus PHY reset.
System Clock. All the device circuits are synchronized to this clock.
System Reset. When low the 77010 and the PHY are reset. This is used as a global line card reset where all
Line Card reset. When low the 77010 and the PHY are reset. This is a local line card reset used to reset a
UTOPIA bus receive clock.
UTOPIA bus receive start of cell.
UTOPIA bus receive enable.
UTOPIA bus receive cell available.
UTOPIA bus receive data bit.
UTOPIA bus receive data bit.
UTOPIA bus receive data bit.
UTOPIA bus receive data bit.
UTOPIA bus receive data bit.
UTOPIA bus receive data bit.
UTOPIA bus receive data bit.
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Description
June 24, 2002