CA91C142D-33CEV IDT, Integrated Device Technology Inc, CA91C142D-33CEV Datasheet
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Universe IID/IIB Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 User Manual TM February 24, 2011 6024 Silver Creek Valley Road, San Jose, California 95138 ©2011 Integrated Device Technology, Inc. ® ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility ...
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Contents 1. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PCI Interface ...
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Contents 5.4 Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Resets, Clocks and Power-up Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 ...
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Contents B.3.1 Coupled Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Universe II User Manual February 24, 2011 Contents Integrated Device Technology www.idt.com ...
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Figures Figure 1: Universe II Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 43: Power-up Configuration Using Active Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tables Table 1: VMEbus Address Modifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 43: Mapping of 32-bit Little-Endian PCI Bus to 64-bit VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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About this Document This section discusses the following topics: • “Scope” on page 13 • “Document Conventions” on page 13 • “Revision History” on page 15 Scope The Universe IID/IIB User Manual discusses the features, capabilities, and configuration requirements for ...
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Object Size Notation • A byte is an 8-bit object. • A word is a 16-bit object. • A doubleword (Dword 32-bit object. • A quadword is a 64-bit (8 byte) object. • A Kword is 1024 ...
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About this Document Revision History February 24, 2011, Formal This document fixed several minor errors. No technical changes were made. May 12, 2010, Formal This document fixed a number of minor typographical errors. No technical changes were made. October 2009, ...
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Universe II User Manual February 24, 2011 About this Document Integrated Device Technology www.idt.com ...
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Functional Overview This chapter outlines the functionality of the Universe II. This chapter discusses the following topics: • “Overview” on page 17 • “VMEbus Interface” on page 22 • “PCI Bus Interface” on page 22 • “Interrupter and Interrupt ...
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Figure 1: Universe II Block Diagram 1.1.1 Universe II Features The Universe II has the following features: • Industry-proven, high performance 64-bit VMEbus interconnect • Fully compliant, 32-bit or 64-bit, 33 MHz PCI bus interconnect • Integral FIFOs for ...
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Functional Overview > Overview • Commercial, industrial, and extended temperature variants • IEEE 1149.1 JTAG • Available packaging: — 35mm x 35mm, 313-contact plastic BGA (PBGA) package 1.1.2 Universe II Benefits The Universe II offers the following benefits to ...
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Figure 2: Universe II In Single Board Computer Application Pr ocessor 1.2 Main Interfaces The Universe II has two main interfaces: the PCI Bus Interface and the VMEbus Interface. Each of the interfaces, VMEbus and PCI bus, there are ...
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Functional Overview > Main Interfaces Figure 3: Universe II Data Flow Diagram PCI Bus Interface PCI Master PCI PCI Slave BUS PCI Interrupts Integrated Device Technology www.idt.com DMA Channel VMEbus DMA bidirectional FIFO Interface VMEbus Slave Channel VME posted ...
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VMEbus Interface The VME Interface is a VME64 Specification compliant interface. 1.2.1.1 Universe II as VMEbus Slave The Universe II VMEbus Slave Channel accepts all of the addressing and data transfer modes documented in the VME64 Specification - ...
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Functional Overview > Main Interfaces 1.2.2.1 Universe II as PCI Target Read transactions from the PCI bus are always processed as coupled transactions. Write transactions can be either coupled or posted, depending upon the setting of the PCI bus ...
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VMEbus Interrupt Handling A VMEbus interrupt triggers the Universe II to generate a normal VMEbus IACK cycle and generate the specified interrupt output. When the IACK cycle is complete, the Universe II releases the VMEbus and the interrupt ...
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VMEbus Interface This chapter explains the operation of the VMEbus Interface.This chapter discusses the following topics: • “VMEbus Requester” on page 25 • “Universe II as VMEbus Master” on page 28 • “Universe II as VMEbus Slave” on page ...
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PCI Target Channel The PCI Target Channel requests the VMEbus Master Interface to service the following conditions: • TXFIFO contains a complete transaction • A coupled cycle request 2.2.1.3 DMA Channel The DMA Channel requests the VMEbus Master ...
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VMEbus Interface > VMEbus Requester In the default setting of Demand mode, the requester asserts its bus request regardless of the state of the BRn* line. By requesting the bus frequently, requesters far down the daisy chain may be ...
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DMA operation, • the DMA VMEbus Tenure Byte Counter has expired, or • DMA block is complete. Refer to “FIFO Operation and Bus Ownership” on page 101 for more information. Universe ...
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VMEbus Interface > Universe II as VMEbus Master Table 1: VMEbus Address Modifier Codes Address Modifier 0x3B 0x3A 0x39 0x38 0x37 0x35 0x34 0x32 0x2F 0x2D 0x2C 0x29 0x21 0x20 0x10 - 0x1F 0xF 0xE 0xD 0xC 0xB 0xA ...
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The Universe II generates Address-Only-with-Handshake (ADOH) cycles in support of lock commands for A16, A24, and A32 spaces. ADOH cycles can only be generated through the Special Cycle Generator (see There are two User Defined AM codes that can ...
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VMEbus Interface > Universe II as VMEbus Master BLT/MBLT cycles are initiated on the VMEbus if the PCI target image has been programmed with this capacity (see “PCI Bus Target Images” on page VMEbus is determined by the initiating ...
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Universe II as VMEbus Slave This section describes the VMEbus Slave Channel and other aspects of the Universe II as VMEbus slave. The Universe II becomes VMEbus slave when one of its eight programmed slave images or register ...
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VMEbus Interface > Universe II as VMEbus Slave A coupled cycle with multiple data beats (such as block transfers) on the VMEbus side is always mapped to single data beat transactions on the PCI bus, where each data beat ...
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Unlike the PCI Target Channel (see “Universe II as PCI Target”), the VMEbus Slave Channel does not retry the VMEbus if the RXFIFO does not have enough space to hold an incoming VMEbus write transaction. Instead, the DTACK* response ...
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VMEbus Interface > Universe II as VMEbus Slave Without prefetching, block read transactions from a VMEbus master are handled by the VMEbus Slave Channel as coupled reads. This means that each data phase of the block transfer is translated ...
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On the PCI bus, prefetching continues as long as there is room for another transaction in the RDFIFO and the initiating VMEbus block read is still active. The space required in the RDFIFO for another PCI burst read transaction ...
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VMEbus Interface > Universe II as VMEbus Slave The Universe II accepts ADOH cycles in any of the slave images when the Universe II PCI Master Interface is enabled (BM bit in PCI_CSR register) and the images are programmed ...
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Location Monitors Universe II has four location monitors to support a VMEbus broadcast capability. The location monitors’ image is a 4-Kbyte image in A16, A24 or A32 space on the VMEbus. If enabled, an access to a location ...
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VMEbus Interface > Universe II as VMEbus Slave 2.4.8.1 Generating Configuration Type 0 Cycles The Universe II asserts one of AD[31:11] on the PCI bus to select a device during a configuration Type 0 access. To perform a configuration ...
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Table 2: PCI Address Line Asserted as a Function of VA[15:11] a VA[15:11] 01111 10000 10001 10010 10011 10100 a. The other values of VA[15:11] are not defined and must not be used. b. Only one of AD[31:11] is ...
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VMEbus Interface > VMEbus Configuration 2.5 VMEbus Configuration The Universe II provides the following functions to assist in the initial configuration of the VMEbus system: • First Slot Detector • Register Access at Power-up • Auto Slot ID (two ...
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Automatic Slot Identification The Universe II supports two types of Auto ID functionality. One type uses the Auto Slot ID technique as described in the VME64 Specification. The other type uses a proprietary method developed by DY4 Systems ...
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VMEbus Interface > Automatic Slot Identification The Universe II can be programmed so that it does not release SYSFAIL* until the SYSFAIL bit in the “VMEbus CSR Bit Clear Register (VCSR_CLR)” on page 329 SYSFAIL* is asserted if the ...
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Figure 5: Timing for Auto-ID Cycle SYSCLK AS* DS0 IACK IACKOUT (CARD 1) IACKOUT (CARD 2) IACKOUT (CARD 3) ID COUNTER 0 VALUE Because all boards are four clocks wide, the value in the clock counter is divided by ...
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VMEbus Interface > Automatic Slot Identification These modes are selected with the VARB bit in the page 275. 2.6.3.3 Fixed Priority Arbitration Mode (PRI) In this mode, the order of priority is VRBR_[3], VRBR_[2], VRBR_[1], and VRBR_[0] as defined ...
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Bus Isolation Mode (BI-Mode) ® BI-Mode is a mechanism for logically isolating the Universe II from the VMEbus. This mechanism is useful for the following purposes: • Implementing hot-standby systems — A system may have two identically configured ...
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VMEbus Interface > Automatic Slot Identification • Clear the BI bit in the MISC_CTL register. — This is effective only if the source of the BI-Mode is no longer active. If VRIRQ_ [1] is still being asserted while the ...
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Universe II User Manual February 24, 2011 2. VMEbus Interface > Automatic Slot Identification Integrated Device Technology www.idt.com ...
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PCI Interface Peripheral Component Interconnect (PCI bus protocol that defines how devices communicate on a peripheral bus and with a host processor device is referred to as PCI compliant it must be compliant with the ...
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Each of the Universe II’s VMEbus slave images can be programmed so that VMEbus transactions are mapped to a 64-bit data bus on the PCI Interface through the LD64EN bit, in the Control Register (DCTL)” on page bus data ...
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PCI Interface > PCI Cycles The command signals (on the C/BE_ lines) contain information about Memory space, cycle type and whether the transaction is read or write. Table 3 shows the PCI command type encoding implemented with the Universe ...
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PCI targets must assert DEVSEL_ if they have decoded the access. During a Configuration cycle, the target is selected by its particular ID Select (IDSEL target does not respond with DEVSEL_ within six clocks, a Master-abort is ...
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PCI Interface > Universe II as PCI Master 3.2.6 Parity Checking The Universe II both monitors and generates parity information using the PAR signal. The Universe II monitors PAR when it accepts data as a master during a read ...
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Arbitration between the two channels for the PCI Master Interface follows a round robin protocol. Each channel is given access to the PCI bus for a single transaction. Once that transaction completes, ownership of the PCI Master Interface is ...
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PCI Interface > Universe II as PCI Master 3.3.2 PCI Burst Transfers The Universe II generates aligned burst transfers of some maximum alignment, according to the programmed PCI aligned burst size (PABS field in the page 271). The PCI ...
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If the error occurs during a posted write to the PCI bus (see also Universe II uses the command information for the transaction (CMDERR [3:0]) and the address of the errored transaction is latched in the “PCI Address Error ...
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PCI Interface > Universe II as PCI Target 3.4 Universe II as PCI Target The Universe II becomes PCI bus target when one of its nine programmed PCI target images, or one of its registers, is accessed by a ...
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Figure 6: PCI Bus Target Channel Dataflow PCI BUS SLAVE INTERFACE The PCI bus and the VMEbus can have different data width capabilities. The maximum VMEbus data width is programmed into the PCI target image through the VDW bit ...
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PCI Interface > Universe II as PCI Target By default, all PCI target images are set for coupled transfers. Coupled transfers typically cause the Universe through three phases: the Coupled Data-Transfer Phase, and then the Coupled ...
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Posted Writes Posted writes are enabled for a PCI target image by setting the PWEN bit in the control register of the PCI target image (see transactions are relayed from the PCI bus to the VMEbus through a ...
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PCI Interface > Universe II as PCI Target Any PCI master attempting coupled transactions is retried while the TXFIFO contains data. If posted writes are continually written to the PCI Target Channel by another master, and the FIFO does ...
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The Special Cycle Generator is configured through the register fields shown in Table 7. Figure 7: Register Fields for the Special Cycle Generator Field 32-bit address PCI Address Space Special cycle 32-bit enable 32-bit compare 32-bit swap The following ...
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PCI Interface > Universe II as PCI Target Once the RMW cycle completes, the VMEbus read data is returned to the waiting PCI bus master and the PCI cycle terminates. RMW Constraints Certain restrictions apply to the use of ...
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VOWN_ACK bit in the MAST_CTL register is a value generate an ADOH cycle with the Special Cycle Generator 5. perform transactions to be locked on the VMEbus 6. release the VMEbus by ...
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PCI Interface > Universe II as PCI Target 3.4.7 Terminations The Universe II performs the following terminations as PCI target: 1. Target-Disconnect • When registers are accessed with FRAME_ asserted (no bursts allowed to registers) • After the first ...
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Universe II User Manual February 24, 2011 3. PCI Interface > Universe II as PCI Target Integrated Device Technology www.idt.com ...
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Slave Image Programming This chapter describes the Slave Image Programming functionality of the Universe II. This chapter discusses the following topics: • “VME Slave Image Programming” on page 67 • “PCI Bus Target Images” on page 70 • “Special ...
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Table 5: PCI Bus Fields for VMEbus Slave Image Field Translation offset Address space RMW Table 6: Control Fields for VMEbus Slave Image Field Image enable Posted write Prefetched read Enable PCI D64 The Bus Master Enable (BM) bit ...
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Slave Image Programming > VME Slave Image Programming 4.2.2 PCI Bus Fields The PCI bus fields specify how the VMEbus transaction is mapped to the appropriate PCI bus transaction. The translation offset field allows the user to translate the ...
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If the LD64EN bit is set, the Universe II generates 64-bit transactions on the PCI bus by asserting REQ64_. The REQ64_ line is asserted during the address phase in a 64-bit PCI system, and is the means of determining ...
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Slave Image Programming > PCI Bus Target Images Table 9: Control Fields for PCI Bus Target Image Field Image enable Posted write IDT recommends that the attributes in a target image not be changed while data is enqueued in ...
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Figure 9: Address Translation Mechanism for PCI Bus to VMEbus Transfers Translations beyond the 4 Gbyte limit will wrap around to the low address range. The Universe II provides support for user defined AM codes. The (USER_AM)” on page ...
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Slave Image Programming > Special PCI Target Image 4.3.3 Control Fields The control fields enable a PCI target image (the EN bit), as well as specify how writes are processed. If the PWEN bit is set, then the Universe ...
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The special PCI target image provides access to all of A16 and most of A24 space (all except the upper 64 Kbytes). By using the special PCI target image for A16 and A24 transactions possible to free ...
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Registers Overview The Universe II Control and Status Registers (UCSR) occupy 4 Kbytes of internal memory. This chapter discusses the following topics: • “Register Access from the PCI Bus” on page 76 • “Register Access from the VMEbus” on ...
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Figure 11: Universe II Control and Status Register Space VMEbus Configuration and Status Registers UNIVERSE DEVICE SPECIFIC REGISTERS PCI CONFIGURATION 5.2 Register Access from the PCI Bus There are different mechanisms to access the UCSR space from the PCI ...
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Registers Overview > Register Access from the PCI Bus Figure 12: PCI Bus Access to UCSR as Memory or I/O Space Accessible through PCI Configuration Cycle 5.2.2 Memory or I/O Access Two 4-Kbyte ranges of addresses in PCI Memory ...
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The SPACE bit of the PCI_BSx registers specifies whether the address lies in Memory space or I/O space. The SPACE bit of these two registers are read-only. There is a power-up option that determines the value of the SPACE ...
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Registers Overview > Register Access from the VMEbus 5.3 Register Access from the VMEbus There are two mechanisms to access the UCSR space from the VMEbus. One method uses a VMEbus Register Access Image (VRAI) which can put the ...
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Figure 13: UCSR Access from the VMEbus Register Access Image VMEbus Configuration and Status Registers (VCSR) UNIVERSE DEVICE SPECIFIC REGISTERS (UDSR) PCI CONFIGURATION SPACE (PCICS) 5.3.2 CR/CSR Accesses The VME64 Specification assigns a total of 16 Mbytes of CR/CSR ...
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Registers Overview > Register Access from the VMEbus For CSRs not supported in the Universe II and for CR accesses, the LAS field in the VCSR_CTL register specifies the PCI bus command that is generated when the cycle is ...
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Figure 14: UCSR Access in VMEbus CR/CSR Space Mapped to PCI Universe II User Manual February 24, 2011 5. Registers Overview > Register Access from the VMEbus VMEbus Configuration and Status Registers (VCSR) UNIVERSE DEVICE SPECIFIC REGISTERS 4 Kbytes ...
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Registers Overview > Mailbox Registers 5.4 Mailbox Registers The Universe II has four 32-bit mailbox registers which provide an additional communication path between the VMEbus and the PCI bus (see Register (MBOX3)” on page may be enabled to generate ...
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An example of a use of the semaphore involves gating access to the Special Cycle Generator Cycle Generator” on page Cycle Generator on an address, no other process accesses this address. Before performing a Special Cycle, a process would ...
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DMA Controller Direct memory access (DMA) allows a transaction to occur between two devices without involving the host processor (for example, a read transaction between a peripheral device and host processor memory). Because less time is required to complete ...
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A final register contains status and control information for the transfer. While the DMA is active, the registers are locked against any changes so that any writes to the registers will have no impact. In direct-mode operation, these registers ...
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DMA Controller > DMA Registers 6.2.2 Non-incrementing DMA Mode The VMEbus Non-Incrementing Mode (Non-Inc Mode) enables the DMA Controller to perform transfers to or from a fixed VMEbus address. This means that the specified VMEbus address is not incremented ...
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The different settings are detailed in Table 14. Table 14: VON Settings for Non-Inc Mode VON 001 010 011 100 101 110 111 P_ERR Flag Behavior When the GO bit is set in Non-Inc Mode, the P_ERR flag of ...
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DMA Controller > DMA Registers 6.2.3 Transfer Size The DMA can be programmed through the to transfer any number of bytes from 1 byte to 16 MBytes. There are no alignment requirements to the source or destination addresses. If ...
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The Universe II can perform data transfers smaller than that programmed in the VDW field in order to bring itself into alignment with the programmed width. For example if the width is set for D32 and the starting VMEbus ...
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DMA Controller > DMA Registers If the DMA has been terminated (stopped, halted, or error), all DMA registers contain values indicating where the DMA terminated. Once all status bits have been cleared, the DMA may be restarted from where ...
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See “DMA Channel Interactions with Other Channels” on page 105 mechanisms which can delay the DMA Channel from acquiring the VMEbus or the PCI bus. 6.2.6.3 DMA Completion and Termination Normally, the DMA continues processing its transfers and command ...
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DMA Controller > Direct Mode Operation When the DMA terminates, an interrupt may be generated to VMEbus or PCI bus. The user has control over which DMA termination conditions cause the interrupt through the INT_STOP, INT_HALT, INT_DONE, INT_LERR, INT_VERR, ...
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Figure 15: Direct Mode DMA transfers Universe II User Manual February 24, 2011 Step 1: Program DGCS with tenure and interrupt requirements Step 2: Program source/destination addresses, & transfer size/attributes Step 3: Ensure status bits are clear Step 4: ...
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DMA Controller > Direct Mode Operation In Step 1, the “DMA General Control/Status Register (DGCS)” on page • The CHAIN bit is cleared, VON and VOFF are programmed with the appropriate values for controlling DMA VMEbus tenure, and the ...
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When the software has detected completion, it must verify the status bits in the DGCS register to see the reason for completion. If one of the error bits have been set it proceeds into an error handling routine (see ...
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DMA Controller > Linked-list Mode Figure 16: Command Packet Structure and Linked List Operation Register information copied to DMA Control and Address Registers DCPP points to next command packet in Linked-List The NULL bit indicates the termination of the ...
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Figure 17: DMA Linked List Operation Step 1: Program DGCS with tenure and interrupt Step 2 : Set up linked-list register, program DCPP Step 5 : Await termination In Step 1, the DGCS register is set up • The ...
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DMA Controller > Linked-list Mode In Step 3, Clear the DTBC register and program the DCPP register to point to the first command packet in the list. When using the DMA to perform linked-list transfers important to ...
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In contrast to a halt, the DMA can also be immediately terminated through the STOP_REQ bit. This stops all DMA operations on the source bus immediately, and set the STOP bit in the same register when the last piece ...
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DMA Controller > FIFO Operation and Bus Ownership If a set of linked command packets has already been created with empty packets at the end of new transfers, adding to the end of the current linked list is accomplished ...
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The PCI bus is requested for the current read once 128 bytes are available in the DMAFIFO. The DMA Channel fills the DMAFIFO using PCI read transactions with each transaction broken at address boundaries determined by the programmed PCI ...
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DMA Controller > FIFO Operation and Bus Ownership The DMA can be programmed to limit its VMEbus tenure to fixed block sizes using the VON field in the “DMA General Control/Status Register (DGCS)” on page relinquishes ownership of the ...
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The DMA can be programmed to limit its VMEbus tenure to fixed block sizes using the VON field in the “DMA General Control/Status Register (DGCS)” on page relinquish ownership of the Master Interface at defined address boundaries (see Ownership” ...
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DMA Controller > DMA Channel Interactions with Other Channels Once an enabled DMA interrupt has occurred the corresponding DMA bit in the Interrupt Status Register (LINT_STAT)” on page 244 (VINT_STAT)” on page 251 enable bits have been set. Each ...
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VERR is set if the DMA encounters a bus error on the VMEbus. This is through a detected assertion of BERR* during a DMA cycle. • P_ERR is set if the GO bit in the DGCS register is ...
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DMA Controller > DMA Error Handling The DTBC register contains the number of bytes remaining to transfer on the source side. The Universe II does not store a count of bytes to transfer on the destination side. If the ...
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Universe II User Manual February 24, 2011 6. DMA Controller > DMA Error Handling Integrated Device Technology www.idt.com ...
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Interrupt Generation and Handling An interrupt is a signal informing a program that an event (for example, an error) has occurred. When a program receives an interrupt signal, it temporarily suspends normal processing and diverts the execution of instructions ...
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Figure 18: Universe Interrupt Circuitry LINT [7:0] Figure 18 illustrates the circuitry inside the Universe II Interrupt Channel. The PCI hardware interrupts are listed on the left, and the VMEbus interrupt inputs and outputs are on the right. Internal ...
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Interrupt Generation and Handling > Interrupt Generation 7.2 Interrupt Generation The Universe II has the ability to generate interrupts on both the PCI bus and VMEbus. 7.2.1 PCI Interrupt Generation The Universe II expands on the basic PCI specification ...
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Table 16: Source, Enabling, Mapping, and Status of PCI Interrupt Output Interrupt Source ACFAIL* SYSFAIL* PCI Software Interrupt VMEbus Software IACK VMEbus Error occurred during a posted write PCI Target-Abort or Master-Abort occurred during a posted write DMA Event ...
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Interrupt Generation and Handling > Interrupt Generation All other sources of PCI interrupts are edge-sensitive. The VMEbus source for PCI interrupts actually comes out of the VMEbus Interrupt Handler block and reflects acquisition of a VMEbus STATUS/ID. Therefore, even ...
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Once an interrupt has been received from any of the sources, the Universe II sets the corresponding status bit in the“VMEbus Interrupt Status Register (VINT_STAT)” on page appropriate VMEbus interrupt output signal (if enabled). When a VMEbus interrupt handler ...
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Interrupt Generation and Handling > Interrupt Generation Figure 19: STATUS/ID Provided by Universe II Programmed from VME_STATUS/ID Registers Once the Universe II has provided the STATUS/ interrupt handler during a software initiated VMEbus interrupt, it generates an ...
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Interrupt Handling The Universe II can handle interrupts from both the PCI bus and the VMEbus. 7.3.1 PCI Interrupt Handling All eight PCI interrupt lines, LINT_[7:0], can act as interrupt inputs to the Universe II. They are level-sensitive ...
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Interrupt Generation and Handling > Interrupt Handling When the Universe II receives a STATUS/ID in response to an IACK cycle, it stores that value in one of seven registers. These registers, “VIRQ7 STATUS/ID Register (V7_STATID)” on page each IACK ...
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Internal Interrupt Handling The Universe II's internal interrupts are routed from several processes in the device. There is an interrupt from the VMEbus Master Interface to indicate a VMEbus error, another from the PCI Master Interface to indicate ...
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Interrupt Generation and Handling > Interrupt Handling Figure 20 shows the sources of interrupts, and the interfaces from which they originate. Figure 20: Sources of Internal Interrupts PCI Bus Interface PCI Master PCI Target PCI software interrupt Integrated Device ...
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VMEbus and PCI Software Interrupts It is possible to interrupt the VMEbus and the PCI bus through software. These interrupts may be triggered by writing the respective enable bits. Interrupting the VMEbus Through Software The ...
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Interrupt Generation and Handling > Interrupt Handling Termination of Software Interrupts Any software interrupt can be cleared by clearing the respective bit in the Register (VINT_EN)” on page 248 However, this method is not recommend for VME bus software ...
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VMEbus Ownership Interrupt The VMEbus ownership interrupt is generated when the Universe II acquires the VMEbus in response to programming of the VOWN bit in the MAST_CTL register (MAST_CTL)” on page VMEbus is ensured during an exclusive access ...
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Interrupt Generation and Handling > Interrupt Handling • Access must be within 4 kbytes of the location monitor base address (see Address Register (LM_BS)” on page • It must be in the specified address space When an access to ...
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Universe II User Manual February 24, 2011 7. Interrupt Generation and Handling > Interrupt Handling Integrated Device Technology www.idt.com ...
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Error Handling Errors occur in a system as a result of parity, bus, or internal problems. In order to handle errors so that they have minimum effects on an application, devices have a logic module called an error handler. ...
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Posted Writes The Universe II provides the option of performing posted writes in both the PCI Target Channel and the VMEbus Slave Channel. Once data is written into the RXFIFO or TXFIFO by the initiating master (VMEbus or ...
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Error Handling > Errors on Decoupled Transactions In a posted write from the VMEbus, all data subsequent to the error in the transaction is flushed from the RXFIFO. However, the length of a VMEbus transaction differs from the length ...
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The PERESP and SERR_EN bits in the (PCI_CSR)” on page 172 parity errors are reported through the assertion of PERR_ if the PERESP bit is set. Address parity errors, reported through the SERR_ signal, are reported if both PERESP ...
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Resets, Clocks and Power-up Options This chapter highlights utility functions in the Universe II. This chapter discusses the following topics: • “Resets” on page 129 • “Power-Up Options” on page 135 • “Test Modes” on page 141 • “Clocks” ...
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The Universe II is only reset through hardware. Software can make the Universe II assert its reset outputs. In order to reset the Universe II through software, the Universe II reset outputs must be connected to the Universe II ...
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Resets, Clocks and Power-up Options > Resets Table 20: Software Reset Mechanism Register “VMEbus CSR Bit Clear Register (VCSR_CLR)” on page 329 Integrated Device Technology www.idt.com Name Type RESET R/W Board Reset Reads: 0=LRST_ not asserted 1=LRST_ asserted Writes: ...
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Universe II Reset Circuitry Table 21 on page 132 For example, it shows that in order to reset the clock services (SYSCLK, CLK64 enables, and PLL divider), PWRRST_ must be asserted. PWRRST_ resets all aspects of Universe II ...
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Resets, Clocks and Power-up Options > Resets Figure 21: Reset Circuitry PWRRST _ VRSYSRST _ RST _ VME_RESET _ MISC_CTL Register SW_SYSRST SW_LRST VCSR_CLR and VCSR_SET Registers RESET Notes PWRRST_, options are loaded from pins. On SYSRST ...
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Assertion of VME_RESET_ causes the Universe II to assert VXSYSRST_. Since VME_RESET_ causes assertion of SYSRST*, and since SYSRST* causes assertion of LRST_, tying both VME_RESET_ and LRST_ to RST_ will put the Universe II into permanent reset. If ...
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Resets, Clocks and Power-up Options > Power-Up Options 9.3 Power-Up Options The Universe II can be automatically configured at power-up to operate in different functional modes. These power-up options allow the Universe set in a particular ...
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The PCI Bus Size is loaded on any RST_ event (PCI 2.1 Specification). The majority of the Universe II power-up options are loaded from the VMEbus address and data lines after any PWRRST_ (see the PCI 2.1 Specification) ...
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Resets, Clocks and Power-up Options > Power-Up Options Table 23 shows how the upper bits in the VRAI base address are programmed for A16, A24, and A32 VMEbus register access images. Table 23: VRAI Base Address Power-up Options VRAI_CTL: ...
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Auto-Syscon Detect The VMEbus SYSCON enabling, required by the VMEbus Specification special power-up option in that it does not return to its after-power-up state following RST_ or SYSRST_. The SYSCON option is loaded during a SYSRST* ...
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Resets, Clocks and Power-up Options > Power-Up Options 9.3.1.10 PCI CSR Image Space There is a power-up option (using the VA[1] pin) that determines the value of the SPACE bit of the PCI_BSx registers. At power-up the SPACE bit ...
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The power-up options are subsequently loaded into their respective registers several PCI clock periods after PWRRST_, SYSRST* and RST_ have all been negated. Because of the power-up configuration, the VMEbus buffers are not enabled until several CLK64 periods after ...
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Resets, Clocks and Power-up Options > Test Modes 9.4 Test Modes The Universe II provides two types of test modes: auxiliary modes (NAND tree simulation and High Impedance) and JTAG (IEEE 1149.1). 9.4.1 Auxiliary Test Modes Two auxiliary test ...
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IDCODE register The following required public instructions are supported: BYPASS (3'b111), SAMPLE(3'b100), and EXTEST(3'b000). The optional public instruction IDCODE(3'b011) selects the IDCODE register which returns 32'b01e201d. The following external pins ...
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Signals and Pinout This chapter discusses the following topics: • “VMEbus Signals” on page 144 • “PCI Bus Signals” on page 147 • “Pin-out” on page 151 10.1 Overview The following detailed description of the Universe II signals is ...
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VMEbus Signals Table 26: VMEbus Signals CLK64 Reference Clock – this 64MHz clock is used to generate fixed timing parameters. It requires a 50-50 duty cycle (±20%) with a 5ns maximum rise time. CLK64 is required to synchronize ...
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Signals and Pinout > VMEbus Signals Table 26: VMEbus Signals (Continued) VBGO[3:0]_ VMEbus Bus Grant Outputs – Only one output is asserted at any time, according to the level at which the VMEbus is being granted. VD[31:0]_ VMEbus Data ...
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Table 26: VMEbus Signals (Continued) VOE_ VMEbus Transceiver Output Enable – Used to control transceivers to isolate the Universe II from the VMEbus during a reset or BI-mode. On power-up, VOE_ is high (to disable the buffers). VOE_ is ...
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Signals and Pinout > PCI Bus Signals Table 26: VMEbus Signals (Continued) VSCON_DIR Syscon Direction Control – Transceiver control that allows the Universe II to drive VBCLR_ and SYSCLK. When the Universe II is driving lines on the VMEbus, ...
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Table 27: PCI Bus Signals AD [63:32] PCI Address/Data Bus – Address and data are multiplexed over these pins providing 64-bit address and data capability. C/BE_ [7:0] PCI Bus Command and Byte Enable Lines – Command and byte enable ...
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Signals and Pinout > PCI Bus Signals Table 27: PCI Bus Signals PCI Reset Output – Used to reset PCI resources. PAR Parity – Parity is even across AD [31:0] and C/BE [3:0] (the number of 1s summed across ...
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Table 27: PCI Bus Signals TCK JTAG Test Clock Input – Used to clock the Universe II’s TAP controller. Tie to any logic level if JTAG is not used in the system. TDI JTAG Test Data Input – Used ...
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Signals and Pinout > Pin-out 10.4 Pin-out 10.4.1 313-pin Plastic BGA Package (PBGA vd[22] vd[19] vd[9] vd[5] 2 vd[18] vd[14] vd[13] 3 vd[23] vd[21] vd[20] vd[12] 4 vd[26] VDD vd[15] vd[11] ...
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Universe II User Manual February 24, 2011 10. Signals and Pinout > Pin-out Integrated Device Technology www.idt.com ...
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Electrical Characteristics This chapter discusses the following topics: • “DC Characteristics” on page 153 • “Operating Conditions” on page 160 • “Power Dissipation” on page 161 11.1 DC Characteristics 11.1.1 Non-PCI Characteristics Table 28 specifies the required DC characteristics ...
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Table 28: Non-PCI Electrical Characteristics Symbols Parameters I Input leakage current IH high I Input leakage current IL low I Tristate output leakage OZ 11.1.2 PCI Characteristics Table 29 specifies the required AC and DC characteristics of all PCI ...
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Electrical Characteristics > DC Characteristics Table 29: AC/DC PCI Electrical Characteristics Symbols Parameters ICL Low clamp current SLEWR Output rise slew rate SLEWR Output fall slew rate a. Equation A: Ioh = 11.9 * (Vout - 5.25) * (Vout ...
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Table 30: Pin List and DC Characteristics for Universe II Signals (Continued) Pin Name Pin Number frame# W17 gnt# AE17 idsel AB16 lint# [0] K20 lint# [1] AA5 lint# [2] L9 lint# [3] V6 lint# [4] M4 lint# [5] ...
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Electrical Characteristics > DC Characteristics Table 30: Pin List and DC Characteristics for Universe II Signals (Continued) Pin Name Pin Number tck H12 tdi A13 tdo C13 tmode [0] AA13 tmode [1] AA21 tmode [2] W23 tms C11 trdy# ...
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Table 30: Pin List and DC Characteristics for Universe II Signals (Continued) Pin Name Pin Number vbgi# [0] N21 vbgi# [1] M16 vbgi# [2] N25 vbgi# [3] N23 vbgo# [0] M20 vbgo# [1] L25 vbgo# [2] M18 vbgo# [3] ...
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Electrical Characteristics > DC Characteristics Table 30: Pin List and DC Characteristics for Universe II Signals (Continued) Pin Name Pin Number vrbbsy# M6 vrberr# A7 vrbr# [0] W5 vrbr# [1] U1 vrbr# [2] R3 vrbr# [3] L7 vrirq# [1] ...
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Table 30: Pin List and DC Characteristics for Universe II Signals (Continued) Pin Name Pin Number vxbr [0] G25 vxbr [1] H24 vxbr [2] P24 vxbr [3] G23 vxirq [1] J19 vxirq [2] K24 vxirq [3] K18 vxirq [4] ...
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Electrical Characteristics > Power Dissipation 11.2.1 Absolute Maximum Ratings Table 32: Absolute Maximum Ratings Parameter DC Supply Voltage (VSS to VDD) DC Input Voltage (V DC Current Drain per Pin, Any Single Input or Output DC Current Drain per ...
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Power Sequencing When designing with the Universe II device, care must be taken when powering the device to ensure proper operation. During power-up, no signals must be applied to any Universe II signal pins prior to stable power ...
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Registers This appendix discusses the following topics: • “Overview” on page 163 • “Register Map” on page 164 • “Register Description” on page 171 12.1 Overview The Universe II Control and Status Registers facilitate host system configuration and allow ...
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Bits listed as reserved must be programmed with a value of 0. Reserved bits always read a value of zero. 12.2 Register Map Table 34 lists the Universe II registers by address offset. Table 34: Universe II Register Map ...
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Registers > Register Map Table 34: Universe II Register Map (Continued) Offset 0x120 “PCI Target Image 1 Translation Offset (LSI1_TO)” on page 190 0x124 Reserved 0x128 “PCI Target Image 2 Control (LSI2_CTL)” on page 191 0x12C “PCI Target Image ...
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Table 34: Universe II Register Map (Continued) Offset 0x1B4 “PCI Target Image 5 Control Register (LSI5_CTL)” on page 217 0x1B8 “PCI Target Image 5 Base Address Register (LSI5_BS)” on page 219 0x1BC “PCI Target Image 5 Bound Address Register ...
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Registers > Register Map Table 34: Universe II Register Map (Continued) Offset 0x304 “PCI Interrupt Status Register (LINT_STAT)” on page 244 0x308 “PCI Interrupt Map 0 Register (LINT_MAP0)” on page 246 0x30C “PCI Interrupt Map 1 Register (LINT_MAP1)” on ...
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Table 34: Universe II Register Map (Continued) Offset 0x40C “User AM Codes Register (USER_AM)” on page 276 0x410-0x4F8 Reserved 0x4FC “Universe II Specific Register (U2SPEC)” on page 277 0x500-0xEFC Reserved 0xF00 “VMEbus Slave Image 0 Control Register (VSI0_CTL)” on ...
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Registers > Register Map Table 34: Universe II Register Map (Continued) Offset 0xF4C-0xF60 Reserved 0xF64 “Location Monitor Control Register (LM_CTL)” on page 300 0xF68 “Location Monitor Base Address Register (LM_BS)” on page 302 0xF6C Reserved 0xF70 “VMEbus Register Access ...
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Table 34: Universe II Register Map (Continued) Offset 0xFC4 “VMEbus Slave Image 6 Translation Offset (VSI6_TO)” on page 323 0xFC8 Reserved 0xFCC “VMEbus Slave Image 7 Control (VSI7_CTL)” on page 324 0xFD0 “VMEbus Slave Image 7 Base Address Register ...
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Registers > Register Description 12.3 Register Description The following tables describe the Universe II registers. 12.3.1 PCI Configuration Space ID Register (PCI_ID) Register name: PCI_VID Bits 7 6 31:24 23:16 15:08 07:00 Bits Name 31:16 DID[15:0] Device ID IDT ...
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PCI Configuration Space Control and Status Register (PCI_CSR) Register name: PCI_CSR Bits 7 6 31:24 D_PE S_SERR 23:16 TFBBC 15:08 07:00 WAIT PERESP Bits Name 31 D_PE Detected Parity Error This bit is always set by the Universe ...
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Registers > Register Description Bits Name 26:25 DEVSEL Device Select Timing The Universe medium speed device 24 DP_D Master Data Parity Error The Universe II PCI master interface sets this bit if the Parity Error Response ...
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Bits Name 05 VGAPS VGA Palette Snoop The Universe II treats palette accesses like all other accesses. 0=Disable 04 MWI_EN Memory Write and Invalidate Enable The Universe II PCI master interface never generates a Memory Write and Invalidate command. ...
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Registers > Register Description Bits Name 00 IOS Target IO Enable 0=Disable 1=Enable Integrated Device Technology www.idt.com Description 175 Reset Type Reset by value R/W PWR VME This bit is 1 after reset if the VMEbus Address [13:12] equals ...
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PCI Configuration Class Register (PCI_CLASS) Register name: PCI_CLASS Bits 7 6 31:24 23:16 15:08 07:00 Bits Name 31:24 BASE [7:0] Base Class Code The Universe II is defined as a PCI bridge device 23:16 SUB [7:0] Sub Class ...
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Registers > Register Description 12.3.4 PCI Configuration Miscellaneous 0 Register (PCI_MISC0) The Universe II is not a multi-function device. Register name: PCI_MISC0 Bits 7 6 31:24 BISTC SBIST 23:16 MFUNCT 15:08 07:00 Bits Name 31 BISTC The Universe II ...
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PCI Configuration Base Address Register (PCI_BS0) This register specifies the 4 Kbyte aligned base address of the 4 Kbyte Universe II register space on PCI. Register name: PCI_BS0 Bits 7 6 31:24 23:16 15:08 07:00 Bits Name 31:12 ...
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Registers > Register Description 12.3.6 PCI Configuration Base Address 1 Register (PCI_BS1) This register specifies the 4 KByte aligned base address of the 4 KByte Universe II register space in PCI Register name: PCI_BS1 Bits 7 6 31:24 23:16 ...
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PCI Configuration Miscellaneous 1 Register (PCI_MISC1) Register name: PCI_MISC1 Bits 7 6 31:24 23:16 15:08 07:00 Bits Name 31:24 MAX_LAT [7:0] Maximum Latency: This device has no special latency requirements 23:16 MIN_GNT [7:0] Minimum Grant 250 ns increments ...
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Registers > Register Description 12.3.8 PCI Target Image 0 Control (LSI0_CTL) In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the ...
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Bits Name 18:16 VAS VMEbus Address Space 000=A16 001=A24 010=A32 011= Reserved 100=Reserved 101=CR/CSR 110=User1 111=User2 15 Reserved Reserved 14 PGM Program/Data AM Code 0=Data 1=Program 13 Reserved Reserved 12 SUPER Supervisor/User AM Code 0=Non-Privileged 1=Supervisor 11:09 Reserved Reserved ...
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Registers > Register Description 12.3.9 PCI Target Image 0 Base Address Register (LSI0_BS) The base address specifies the lowest address in the address range that will be decoded. The base address for PCI Target Image 0 and PCI Target ...
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PCI Target Image 0 Bound Address Register (LSI0_BD) The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register. If the bound address is ...
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Registers > Register Description 12.3.11 PCI Target Image 0 Translation Offset (LSI0_TO) The translation offset for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution. PCI Target Images and 7 ...
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PCI Target Image 1 Control (LSI1_CTL) In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed ...
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Registers > Register Description Bits Name 18:16 VAS VMEbus Address Space 000=A16 001=A24 010=A32 011= Reserved 100=Reserved 101=CR/CSR 110=User1 111=User2 15 Reserved Reserved 14 PGM Program/Data AM Code 0=Data 1=Program 13 Reserved Reserved 12 SUPER Supervisor/User AM Code 0=Non-Privileged ...
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PCI Target Image 1 Base Address Register (LSI1_BS) The base address specifies the lowest address in the address range that will be decoded. Register name: LSI1_BS Bits 7 6 31:24 23:16 15:08 07:00 Bits Name 31:16 BS[31:16] Base ...
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Registers > Register Description 12.3.14 PCI Target Image 1 Bound Address Register (LSI1_BD) The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register. If ...
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PCI Target Image 1 Translation Offset (LSI1_TO) Address bits [31:16] generated on the VMEbus in response to an image decode are a two’s complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the ...
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Registers > Register Description 12.3.16 PCI Target Image 2 Control (LSI2_CTL) In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the ...
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Bits Name 18:16 VAS VMEbus Address Space 000=A16 001=A24 010=A32 011= Reserved 100=Reserved 101=CR/CSR 110=User1 111=User2 15 Reserved Reserved 14 PGM Program/Data AM Code 0=Data 1=Program 13 Reserved Reserved 12 SUPER Supervisor/User AM Code 0=Non-Privileged 1=Supervisor 11:09 Reserved Reserved ...
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Registers > Register Description 12.3.17 PCI Target Image 2 Base Address Register (LSI2_BS) The base address specifies the lowest address in the address range that will be decoded. Register name: LSI12_BS Bits 7 6 31:24 23:16 15:08 07:00 Bits ...
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PCI Target Image 2 Bound Address Register (LSI2_BD) The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register. If the bound address is ...
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Registers > Register Description 12.3.19 PCI Target Image 2 Translation Offset (LSI2_TO) Address bits [31:16] generated on the VMEbus in response to an image decode are a two’s complement addition of address bits [31:16] on the PCI Bus and ...
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PCI Target Image 3 Control (LSI3_CTL) In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed ...
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Registers > Register Description Bits Name 18:16 VAS VMEbus Address Space 000=A16 001=A24 010=A32 011= Reserved 100=Reserved 101=CR/CSR 110=User1 111=User2 15 Reserved Reserved 14 PGM Program/Data AM Code 0=Data 1=Program 13 Reserved Reserved 12 SUPER Supervisor/User AM Code 0=Non-Privileged ...
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PCI Target Image 3 Base Address Register (LSI3_BS) The base address specifies the lowest address in the address range that will be decoded. Register name: LSI3_BS Bits 7 6 31:24 23:16 15:08 07:00 Bits Name 31:16 BS[31:16] Base ...
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Registers > Register Description 12.3.22 PCI Target Image 3 Bound Address Register (LSI3_BD) The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register. If ...
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PCI Target Image 3 Translation Offset (LSI3_TO) Address bits [31:16] generated on the VMEbus in response to an image decode are a two’s complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the ...