PI7C8150ANDE Pericom Semiconductor, PI7C8150ANDE Datasheet - Page 12
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PI7C8150ANDE
Manufacturer Part Number
PI7C8150ANDE
Description
IC PCI-PCI BRIDGE 2PORT 256-PBGA
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8150ANDE.pdf
(111 pages)
Specifications of PI7C8150ANDE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
06-0057
2
2.1
2.2
2.2.1
SIGNAL DEFINITIONS
Signal Types
Signals
Note: Signal names that end with “_L” are active LOW.
PRIMARY BUS INTERFACE SIGNALS
Signal Type
I
O
P
TS
STS
OD
Name
P_AD[31:0]
P_CBE[3:0]
P_PAR
Pin #
60, 61, 63, 67, 68,
70, 71, 73, 74, 76,
77, 93, 95, 96, 98,
99, 101, 107, 109,
112, 113, 115,
116, 118, 119,
121, 122
64, 79, 92, 110
90
49, 50, 55, 57, 58,
Description
Input Only
Output Only
Power
Tri-State bi-directional
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when
deasserting.
Open Drain
Page 12 of 111
Pin #
N3, T2, T4, N5,
P5, T5, N6, R5,
T6, P7, T7, R7,
T8, P8, R8, T9,
R12, P12, T14,
R13, N12, T15,
P16, N15, M14,
M13, M15,
L13, M16, L14,
L15, L16
R6, R9, T13,
N16
N11
Type
TS
TS
TS
2-PORT PCI-TO-PCI BRIDGE
Description
Primary Address / Data: Multiplexed address and data
bus. Address is indicated by P_FRAME_L assertion.
Write data is stable and valid when P_IRDY_L is
asserted and read data is stable and valid when
P_TRDY_L is asserted. Data is transferred on rising
clock edges when both P_IRDY_L and P_TRDY_L are
asserted. During bus idle, PI7C8150A drives P_AD to a
valid logic level when P_GNT_L is asserted.
Primary Command/Byte Enables: Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. After that, the initiator drives the byte enables
during data phases. During bus idle, PI7C8150A drives
P_CBE[3:0] to a valid logic level when P_GNT_L is
asserted.
Primary Parity. Parity is even across P_AD[31:0],
P_CBE[3:0], and P_PAR (i.e. an even number of 1’s).
P_PAR is an input and is valid and stable one cycle after
the address phase (indicated by assertion of
P_FRAME_L) for address parity. For write data phases,
P_PAR is an input and is valid one clock after
P_IRDY_L is asserted. For read data phase, P_PAR is
an output and is valid one clock after P_TRDY_L is
asserted. Signal P_PAR is tri-stated one cycle after the
P_AD lines are tri-stated. During bus idle, PI7C8150A
drives P_PAR to a valid logic level when P_GNT_L is
asserted.
APRIL 2006 – Revision 1.1
PI7C8150A