PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 28

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

July 2009 – Revision 1.2
Pericom Semiconductor
ADDRESS
54h
55h
56h
57h
60h
62h
64h
66h
70h
72h
74h
76h
80h
82h
84h
86h
90h
92h
PCI CFG OFFSET
84h (Port 2)
84h: Bit [3]
80h (Port 2)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
84h (Port 2)
84h: Bit [31:24]
84h (Port 3)
84h: Bit [3]
80h (Port 3)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
84h (Port 2)
84h: Bit [31:24]
214h (Port 0)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
214h (Port 1)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
214h (Port 2)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
214h (Port 3)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
B0h (Port 0)
B0h – Bit [15:0]
B0h (Port 1)
B0h – Bit [15:0]
B0h (Port 2)
B0h – Bit [15:0]
B0h (Port 3)
B0h – Bit [15:0]
B0h (Port 0)
B0h – Bit [31:16]
B0h (Port 1)
B0h – Bit [31:16]
B0h (Port 2)
B0h – Bit [31:16]
B0h (Port 3)
B0h – Bit [31:16]
B4h (Port 0)
B4h: Bit [31:16]
B4h (Port 1)
B4h: Bit [31:16]
DESCRIPTION
No_Soft_Reset for Port 2
Power Management Capability for Port 2
Power Management Data for Port 2
No_Soft_Reset for Port 3
Power Management Capability for Port 3
Power Management Data for Port 3
Power Budget Register for Port 0
Power Budget Register for Port 1
Power Budget Register for Port 2
Power Budget Register for Port 3
Replay Time-out Counter for Port 0
Replay Time-out Counter for Port 1
Replay Time-out Counter for Port 2
Replay Time-out Counter for Port 3
Acknowledge Latency Timer for Port 0
Acknowledge Latency Timer for Port 1
Acknowledge Latency Timer for Port 2
Acknowledge Latency Timer for Port 3
PHY Parameter for Port 0
PHY Parameter for Port 1
Page 28 of 77
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Bit [0]: No_Soft_Reset
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Bit [15:8] – read only as Data register
Bit [0]: No_Soft_Reset
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Bit [15:8] – read only as Data register
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Bit [15:0]: Relay Time-out Counter
Bit [15:0]: Relay Time-out Counter
Bit [15:0]: Relay Time-out Counter
Bit [15:0]: Relay Time-out Counter
Bit [31:16]: Acknowledge Latency Timer
Bit [31:16]: Acknowledge Latency Timer
Bit [31:16]: Acknowledge Latency Timer
Bit [31:16]: Acknowledge Latency Timer
Bit [31:16]: PHY Parameter
Bit [31:16]: PHY Parameter
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