PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 22

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
3.1
Table 3-1. PCI Transactions
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C8150B, and transaction termination. The PI7C8150B has two 128-byte FIFO’s for
buffering of upstream and downstream transactions. These hold addresses, data,
commands, and byte enables that are used for write transactions. The PI7C8150B also has
an additional four 128-byte FIFO’s that hold addresses, data, commands, and byte enables
for read transactions.
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8150B.
Table 3-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C8150B initiates
transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150B
responds to transactions as a target, on the primary (P) and secondary (S) buses.
PCI BUS OPERATION
As indicated in Table 3-1, the following PCI commands are not supported by
PI7C8150B:
PI7C8150B never initiates a PCI transaction with a reserved command code and, as a
target, PI7C8150B ignores reserved command codes.
PI7C8150B does not generate interrupt acknowledge transactions. PI7C8150B
ignores interrupt acknowledge transactions as a target.
PI7C8150B does not respond to special cycle transactions. PI7C8150B cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
ADVANCE INFORMATION
April 2009 – Revision 1.08
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
PI7C8150B
N
N
Y
Y
N
N
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Secondary
Y
Y