CC-W9M-NA37-XE-B Digi International, CC-W9M-NA37-XE-B Datasheet - Page 32

• Manufacturer Part Number: CC-W9M-NA37-XE-B
• Description: MOD WI-9M 64MB SDRAM 128MB FLASH
• Manufacturer: Digi International
• Series: -r

Specifications of CC-W9M-NA37-XE-B

• Module/board Type: Core Module
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Networking

www.digiembedded.com
SPI interface
Where UBRDIVn is integer part of DIV_VAL - and UDIVSLOTn the floating point part of
DIV_VAL.
For example, if the baud rate is 115200 bps and SRCCLK is 66 MHz, UBRDIVn and
UDIVSLOTn are:
DIV_VAL = (66000000 / (115200 x 16)) -1
= 35.8 -1
= 34.8
* UBRDIVn = 34
(num of 1's in UDIVSLOTn)/16 = 0.8
(num of 1's in UDIVSLOTn) = 12.8=>13
The table below shows the recommended value table of UDIVSLOTn register.
As a result, DIV_VAL = 34.8125 = 34+13x(1/16)
The baud rate is finally:
66000000/(34.8125+1)/16 = 115167.2 baud
The S3C2443 provides two SPI-interfaces, each of which have two 8-bit shift registers
for transmission and receiving, respectively. During an SPI transfer, data is
simultaneously transmitted (shifted out serially) and received (shifted in serially).
Four I/O pin signals are associated with SPI transfers: SCK (SPICLK0,1), MISO
(SPIMISO0,1) data line, MOSI (SPIMOSI0,1) data line, and the active low /SS (nSS0,1)
pin.
Both 4-pin SPI interfaces are provided at the system connector (Clock, Chip-Select,
Data-In and Data-Out). SPI0 interface is located at the general pins of the system
connector, while SPI1 interface shares its pins with interrupt functions at the specific
pins of the system connector.
Num of 1’s
0
1
2
3
4
5
6
7
UDIVSLOTn
0x0000(0000_0000_0000_0000b)
0x0080(0000_0000_0000_1000b)
0x0808(0000_1000_0000_1000b)
0x0888(0000_1000_1000_1000b)
0x2222(0010_0010_0010_0010b)
0x4924(0100_1001_0010_0100b)
0x4A52(0100_1010_0101_0010b)
0x54AA(0101_0100_1010_1010b)
Num of 1’s
8
9
10
11
12
13
14
15
UDIVSLOTn
0x5555(0101_0101_0101_0101b)
0xD555(1101_0101_0101_0101b)
0xD5D5(1101_0101_1101_0101b)
0xDDD5(1101_1101_1101_0101b)
0xDDDD(1101_1101_1101_1101b)
0xDFDD(1101_1111_1101_1101b)
0xDFDF(1101_1111_1101_1111b)
0xFFDF(1111_1111_1100_1111b)
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