MT41J128M8JP-15E:G Micron Technology Inc, MT41J128M8JP-15E:G Datasheet - Page 133
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MT41J128M8JP-15E:G
Manufacturer Part Number
MT41J128M8JP-15E:G
Description
IC DDR3 SDRAM 1GBIT 78FBGA
Manufacturer
Micron Technology Inc
Series
-r
Type
DDR3 SDRAMr
Specifications of MT41J128M8JP-15E:G
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (128M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Organization
128Mx8
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
220mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J128M8JP-15E:G
Manufacturer:
VISHAY
Quantity:
43 000
Company:
Part Number:
MT41J128M8JP-15E:G
Manufacturer:
MICRON32
Quantity:
2 348
Company:
Part Number:
MT41J128M8JP-15E:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT41J128M8JP-15E:G
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT41J128M8JP-15E:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 74: READ (BC4) to WRITE (BC4) OTF
Figure 75: READ to PRECHARGE (BL8)
DQS, DQS#
Command
Command 1
DQS, DQS#
Address
Address 2
CK#
DQ
CK
DQ 3
CK#
CK
Bank a,
READ
Col n
T0
READ
Bank,
Col n
T0
READ-to-WRITE command delay = RL + t CCD/2 + 2 t CK - WL
NOP
T1
Notes:
NOP
T1
NOP
T2
t RAS
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4.
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
t RTP
T2
RL = 5
NOP
T3
NOP
T3
NOP
T4
WRITE
T4
Bank a,
Bank,
(or all)
Col b
PRE
T5
t RPRE
NOP
T5
NOP
T6
DO
n
DO
n + 1
NOP
T6
NOP
T7
n + 2
DO
WL = 5
t RPST
n + 3
DO
NOP
NOP
T8
T7
DO
n
n + 1
DO
NOP
t RP
T9
NOP
T8
n + 2
DO
t WPRE
n + 3
DO
NOP
T10
n + 4
NOP
DO
T9
DI
n
n + 5
DO
n + 1
DI
NOP
T11
n + 6
DO
n + 2
NOP
T10
DI
n + 7
DO
n + 3
t BL = 4 clocks
DI
T12
NOP
t WPST
NOP
T11
Bank a,
Row b
ACT
T13
NOP
T12
T14
NOP
Transitioning Data
NOP
T13
T15
NOP
Transitioning Data
NOP
T14
NOP
T16
t WTR
t WR
Don’t Care
NOP
T15
Don’t Care
NOP
T17