RC28F128J3D75D Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., RC28F128J3D75D Datasheet - Page 27

• Manufacturer Part Number: RC28F128J3D75D
• Description: IC FLASH 128MBIT 75NS 64EZBGA
• Manufacturer: Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
• Series: -r

Specifications of RC28F128J3D75D

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant
• Other names: 872828; 872828TR; 872828TR; RC28F128J3D75 S L8QN; RC28F128J3D75D; RC28F128J3D75DTR

Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Table 12: Write Operations
December 2007
316577-06
Notes:
CE
disables the device (see
1.
2.
3.
4.
5.
6.
7.
8.
9.
W11
W12
W13
W15
W1
W2
W3
W4
W5
W6
W7
W8
W9
#
X
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
t
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
A write operation can be initiated and terminated with either CE
Sampled, not 100% tested.
Write pulse width (t
(whichever goes high first). Hence, t
Refer to
program, or lock-bit configuration.
Write pulse width high (t
low (whichever goes low first). Hence, t
For array access, t
STS timings are based on STS configured in its RY/BY# default mode.
V
0).
t
t
t
t
t
t
t
t
t
WHEH
WHDX
DVWH
AVWH
WHAX
VPWH
WHGL
ELWL
WHRL
PEN
PHWL
Symbol
t
t
should be held at V
t
QVVL
WPH
WP
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
EHWH
PHEL
DVEH
AVEH
EHAX
EHGL
EHRL
EHDX
VPEH
Table 17, “Enhanced Configuration Register” on page 33
C
)
)
)
)
)
)
)
)
)
)
Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on page 31
RP# High Recovery to WE# (CE
CE
Write Pulse Width
Data Setup to WE# (CE
Address Setup to WE# (CE
CE
Data Hold from WE# (CE
Address Hold from WE# (CE
Write Pulse Width High
V
Write Recovery before Read
WE# (CE
V
PEN
PEN
AVQV
X
X
WP
(WE#) Low to WE# (CE
(WE#) Hold from WE# (CE
Setup to WE# (CE
Hold from Valid SRD, STS Going High
) is defined from CE
is required in addition to t
PENH
WPH
X
) High to STS Going Low
) is defined from CE
until determination of block erase, program, or lock-bit configuration success (SR[5:3,1] =
Parameter
WP
WPH
= t
X
X
) Going High
) Going High
X
X
WLWH
) High
X
or WE# going low (whichever goes low last) to CE
= t
) Going High
X
X
) Going Low
) High
WHWL
X
X
X
= t
) High
WHGL
) Going Low
or WE# going high (whichever goes high first) to CE
ELEH
= t
for any accesses after a write.
EHEL
= t
WLEH
= t
X
WHEL
128 Mbit
256 Mbit
= t
Density
32 Mbit
64 Mbit
or WE#.
X
All
high is defined at the first edge of CE0, CE1, or CE2 that
ELWH
= t
EHWL
.
.
Min
150
180
210
210
60
50
55
30
35
Valid for All
0
0
0
0
0
0
for valid A
Speeds
Max
500
IN
X
and D
or WE# going high
IN
Unit
ns
X
for block erase,
or WE# going
1,2,3,8,9
Datasheet
Notes
1,2,3
1,2,4
1,2,4
1,2,5
1,2,5
1,2,6
1,2,3
1,2,7
1,2,8
1,2,
1,2,
1,2,
).
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