MAX14502AETL+T Maxim Integrated Products, MAX14502AETL+T Datasheet - Page 27

• Manufacturer Part Number: MAX14502AETL+T
• Description: IC CARD READER USB-SD 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX14502AETL+T

• Applications: USB
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 40-TQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

sists of two blocks: a clock squarer input (enabled by
default), which accepts low-signal amplitude TCXO sig-
nals (down to 200mV), and a PLL with fixed dividers.
The PLL sub system can be configured using the I
interface. The complete list of PLL subsystem combina-
tions are listed in Table 3.
Table 3. Clock Source Bit Values
Figure 13. START and STOP Conditions
CLKSOURCE
00000b
00001b
00010b
00101b
00110b
01001b
01010b
01101b
01110b
SDA
SCL
CONDITION
START
SOURCE (MHz)
Selector Guide
______________________________________________________________________________________
See Ordering
S
Information/
19.2
19.2
13.0
13.0
12.0
12.0
26.0
26.0
Default low-amplitude
clock
Rail-to-rail square wave
Low-amplitude sine
wave
Rail-to-rail square wave
Low-amplitude sine
wave
Rail-to-rail square wave
Low-amplitude sine
wave
Rail-to-rail square wave
Low-amplitude sine
wave
NOTES
2
C
Hi-Speed USB-to-SD Card
The MAX14500–MAX14503 operate as I
that send and receive data through an I
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master(s) and slave(s). A
master initiates all data transfers to and from the
MAX14500–MAX14503, and generates the SCL clock
that synchronizes the data transfer. The SDA line oper-
ates as both an input and an open-drain output requiring
a pullup resistor on SDA. The SCL line operates only as
an input. A pullup resistor is required on SCL if there are
multiple masters on the 2-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Each transmission consists of a START (S) condition by
a master, followed by the MAX14500–MAX14503’s 7-bit
slave address, plus a R/W bit, a register address byte,
one or more data bytes, and finally a STOP (P) condition.
Both SCL and SDA remain high when the interface is
idle. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high (Figure 13). When the master
has finished communicating with the slave, it issues a
STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
Readers with Bypass
START and STOP Conditions
I
2
C Serial Interface
Serial Addressing
CONDITION
2
STOP
C slave devices
P
2
C-compatible
27