MIC5373-MG4YMT TR Micrel Inc, MIC5373-MG4YMT TR Datasheet - Page 14

• Manufacturer Part Number: MIC5373-MG4YMT TR
• Description: IC REG LDO TRIPLE 150MA 16MLF
• Manufacturer: Micrel Inc
• Series: -r

Specifications of MIC5373-MG4YMT TR

• Regulator Topology: Positive Fixed
• Voltage - Output: 2.8V, 1.8V, 1.2V
• Voltage - Input: 1.7 V ~ 5.5 V
• Voltage - Dropout (typical): 0.17V @ 150mA, 0.275V @ 150mA, 0.275V @ 150mA
• Number Of Regulators: 3
• Current - Output: 150mA
• Current - Limit (min): 200mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-UFQFN Exposed Pad, 16-MLF®
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 576-3911-2

Pin Descriptions
INLDO
The LDO input pins INLDO1/2 and INLDO3 provide the
input power to the linear regulators LDO1, LDO2 and
LDO3. The input operating voltage range is from 1.7V to
5.5V. For input voltages from 1.7V to 2.5V the output
current must be limited to 30mA each. Due to line
inductance a 1µF capacitor placed close to the INLDO
pins and the GND pin is recommended. Please refer to
layout recommendations.
BIAS
The BIAS pin provides power to the internal reference
and control sections of the MIC5373/83. A 0.1µF
ceramic capacitor must be connected from BIAS to GND
for clean operation.
EN (MIC5373)
The enable pins EN1, EN2 and EN3 provide logic level
control for the outputs OUT1, OUT2 and OUT3,
respectively. A logic high signal on an enable pin
activates the respective LDO. A logic low signal on an
enable pin deactivates the respective LDO. Do not leave
the EN pins floating, as it would leave the regulator in an
unknown state.
/EN (MIC5383)
The enable pins /EN1, /EN2 and /EN3 provide logic level
control for the outputs OUT1, OUT2 and OUT3,
respectively. A logic high signal on an enable pin
deactivates the respective LDO. A logic low signal on an
enable pin activates the respective LDO. Do not leave
the EN pins floating, as it would leave the regulator in an
unknown state.
OUT
OUT1, OUT2 and OUT3 are the output pins of each
LDO. A minimum of 1µF capacitor be placed as close as
possible to each of the OUT pins. A minimum voltage
rating of 6.3V is recommended for each capacitor.
GND
The GND pin is the ground path for the control circuitry
and the power ground for all LDOs. The current loop for
the ground should be kept as short as possible. Refer to
the layout recommendations for more details.
POR
The POR (power-on-reset) pin is an open drain output. A
resistor (10kΩ to 100kΩ) can be used for a pull up to
either the input or the output voltage of the regulator.
POR is asserted high when the voltage at DLY reaches
1.25V. A delay can be added by placing a capacitor from
Micrel, Inc.
July 2010
14
the DLY pin to ground.
POR_IN
The POR_IN (power-on-reset input) pin compares any
voltage to an internal 0.9V reference. This function can
be used to monitor any of the LDO outputs or any
external voltage rail. When the monitored voltage is
greater than 0.9V, the POR_IN flag will internally trigger
a 1.25µA source current to charge the external capacitor
at the DLY pin. A resistor divider network may be used
to divide down the monitored voltage to be compared
with the 0.9V at the POR_IN. This resistor network can
change the trigger point to any voltage level. A small
decoupling capacitor is recommended between POR_IN
and ground to reject high frequency noise that might
interfere with the POR circuit. Do not leave the POR_IN
pin floating.
DLY
The delay pin is used to set the POR delay time. Adding
a capacitor to this pin adjusts the delay of the POR
signal. When the POR_IN flag is triggered, a constant
1.25µA current begins to charge the external capacitor
tied to the DLY pin. When the capacitor reaches 1.25V
the POR will be pulled high by the external pull up
resistor. The equation to calculate the charge time is
shown:
The delay time (t) is in seconds, the delay voltage is
1.25V internally, and the external delay capacitance
(C
delay time will be 1 second. A capacitor at the DLY pin is
recommended when the POR function is used in order to
prevent unexpected triggering of the POR signal in noisy
systems.
MR
The MR (manual reset) pin resets the output of POR and
DLY generator regardless if the monitored voltage is in
regulation or not. Applying a voltage greater than 1.2V
on the MR pin will cause the POR voltage to be pulled
low. When a voltage below 0.2V is applied to the MR
pin, the internal 1.25µA will begin to charge the DLY pin
until it reaches 1.25V.
1.25V, the POR voltage will be pulled high by the pull up
external resistor again. Do not leave the MR pin floating.
DLY
) is in microfarads. For a 1µF delay capacitor, the
t
Delay
(s)
=
⎛
⎜
⎝
1.25V
. 1
25
When the DLY pin reaches
x
x
10
C
−6
DLY
⎞
⎟
⎠
M9999-070110
MIC5373/83