DS33W41+ Maxim Integrated Products, DS33W41+ Datasheet - Page 36

• Manufacturer Part Number: DS33W41+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33W41+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2
The SPI interface is a four-signal serial interface that allows configuration and monitoring of the device with a
minimal number of electrical connections. The SPI interface uses Full-Duplex SPI Slave operation. The maximum
clock frequency of the SPI interface is 10MHz. Each access (read or write) takes approximately 2.4μs. With two
Address/Control bytes required for each data byte, the maximum data throughput rate is approximately 3.3
megabits per second. See the Section 11.1 for functional timing diagrams, and Section 12 for AC parametric
timing. Note that the parallel bus is not available in the 144-pin DS33X11, and the SPI Slave port must be used for
processor control.
The SPI bus is implemented using four signals: Clock (SPI_CLK), Master-Out Slave-In data (SPI_MOSI), Master-In
Slave-Out data (SPI_MISO), and Chip Select (CS). SPI_CLK polarity and phase can be set by the SPI_CPOL and
SPI_CPHA pins. The order of the address and data bits in the serial stream is selectable using the SPI_SWAP pin.
The Read/Write (R/W) bit is always the first bit and the Burst (B) bit is always last bit of the Address/Control Bytes
and their location is not affected by the SPI_SWAP pin setting.
Note that SPI “Burst mode” is not applicable for OAM frame insertion or extraction, due to the indirect access of the
extract and insert queues. The interface overhead associated with frame insertion and extraction is 5 register
accesses per frame.
The SPI protocol defines four combinations of SCK phase and polarity with respect to the data controlled by CPOL
(clock polarity) and CPHA (clock phase):
SPI_CPOL SPI_CPHA
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0
1
0
1
SPI Serial Processor Interface
0
0
1
1
SPI_CLK transitions at beginning of bit timing.
SPI_CLK transitions at beginning of bit timing.
SPI_CLK transitions in middle of bit timing.
SPI_CLK transitions in middle of bit timing.
SPI_CLK falling-edge transfer.
SPI_CLK falling-edge transfer.
SPI_CLK rising-edge transfer.
SPI_CLK rising-edge transfer.
Transfer
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