SEG01G72A1BH1MT-37R Swissbit NA Inc, SEG01G72A1BH1MT-37R Datasheet - Page 2

• Manufacturer Part Number: SEG01G72A1BH1MT-37R
• Description: DRAM DDR2 1GB 200-SORDIMM W/ECC
• Manufacturer: Swissbit NA Inc
• Series: -r

Specifications of SEG01G72A1BH1MT-37R

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 533MHz
• Features: -
• Package / Case: 200-SORDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1043

This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Registered Dual-In-line
Memory Module (So-RDIMM) which is organized as x72 high speed CMOS memory arrays. A Register
component and a PLL chip reduce loading on the clock and command/address bus. The module uses DDR2
SDRAM devices with eight internal banks. The module uses double data rate to achieve high-speed operation.
DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2
SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge
function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The
DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high
effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All inputs and all
full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I
utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Timing Parameters
Pin Name
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
A0 - A13
BA0 – BA2
DQ0 – DQ63
DM0-DM8
RAS#
CAS#
WE#
CKE0 / CKE1
CK0
CK0#
DQS0 – DQS8
DQS0# - DQS8#
S0# / S1#
Reset#
CB0 – CB7
Organization
SEG02G72B1BH2MT-30[W]R
SEG02G72B1BH2MT-37[W]R
256M x 72bit
Part Number
18 x 128M x 8bit (1024Mbit)
2
C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
DDR2 SDRAMs used
67.6 (long) x 30.0(high) x 3.80 [max] (thickness)
Address Inputs
Bank Address Inputs
Data Input / Output
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQs are High-Z.
Check Bits
Fon: [phone]
Fax: [phone]
Module Density
2 GB
2 GB
Module Dimensions
Data Sheet
Addr.
Row
14
in mm
Transfer Rate
BA0, BA1, BA2
5.3 GB/s
4.2 GB/s
Device Bank
www.swissbit.com
eMail: [e-mail]
Addr.
Clock Cycle/Data bit
Column
Addr.
3.75ns/533MT/s
3.0ns/667MT/s
10
Rev.1.0
rate
Refresh
8k
30.07.2010
Bank Select
S0#, S1#
Module
Latency
5-5-5
4-4-4
Page 2
of 14