MT18HTF51272AZ-667C1 Micron Technology Inc, MT18HTF51272AZ-667C1 Datasheet - Page 10

• Manufacturer Part Number: MT18HTF51272AZ-667C1
• Description: MODULE DDR2 SDRAM 4GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HTF51272AZ-667C1

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 667MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IDD Specifications
Table 10: DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
PDF: 09005aef83c6d17f
htf18c128_256_512x72az.fm - Rev. C 12/10 EN
Parameter
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
(I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-
ing
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; BL
= 4, CL = CL (I
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read, I
= 0mA; BL = 4, CL = CL (I
(I
ing; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
RAS =
DD
DD
DD
DD
), AL = 0;
); CKE is LOW; Other control and address bus inputs are stable;
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
t
RP =
t
RAS MIN (I
t
RP (I
t
DD
CK =
), AL = 0;
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
t
DD
CK (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
Specifications and Conditions – 1GB (Die Revision G)
DD
DD
DD4W
t
t
CK =
CK =
),
), AL = 0;
t
RC =
t
t
CK (I
CK (I
t
RC (I
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM UDIMM
DD
t
DD
CK =
); REFRESH command at every
),
DD
t
RAS =
),
t
CK (I
t
RAS =
DD
t
RAS MAX (I
),
t
CK =
t
RAS MIN (I
t
t
RAS =
CK =
t
CK =
t
CK =
t
CK (I
t
t
OUT
CK (I
CK =
t
t
t
CK (I
RAS MAX (I
CK =
DD
10
t
DD
CK
= 0mA; BL = 4, CL = CL
DD
),
DD
),
t
DD
t
),
CK (I
RP =
t
),
t
CK (I
); CKE is HIGH, S# is
RAS =
t
RCD =
t
RC =
t
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RFC (I
t
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
RP (I
DD
); CKE is LOW;
t
); CKE is
t
RAS MAX
),
RC (I
t
RCD (I
DD
DD
t
RP =
); CKE is
) inter-
DD
DD
),
t
OUT
RP
);
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
© 2009 Micron Technology, Inc. All rights reserved.
IDD Specifications
-80E/
-800
1188
1143
648
738
126
432
504
324
162
594
918
126
1098
1053
-667
603
693
126
396
450
270
162
540
873
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA