AD7569JR Analog Devices Inc, AD7569JR Datasheet - Page 11
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AD7569JR
Manufacturer Part Number
AD7569JR
Description
IC I/O PORT 8BIT ANLG 24-SOIC
Manufacturer
Analog Devices Inc
Series
LC²MOSr
Datasheet
1.AD7569JRZ.pdf
(20 pages)
Specifications of AD7569JR
Rohs Status
RoHS non-compliant
Applications
Analog I/O
Interface
Bus
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
24-SOIC (7.5mm Width)
Mounting Type
Surface Mount
Converter Type
ADC/DAC
Resolution
8b
Number Of Dac's
Single
Data Rate
0.5MSPS
Digital Interface Type
Parallel
Pin Count
24
Package Type
SOIC W
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD7569JRZ
Manufacturer:
Renesas
Quantity:
111
Part Number:
AD7569JRZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
RESET line, the DAC output resets to 0 V when the entire
system is reset. Figure 7 shows the input control logic for the
AD7569 DAC; the write cycle timing diagram is shown in
Figure 8.
DAC Timing and Control—AD7669
Table III shows the truth table for the dual DAC operation of
the AD7669. The part contains two 8-bit DAC registers that are
loaded from the data bus under the control of CS, A/B and WR.
Address line A/B selects which DAC register the data is
loaded to. The data contained in the DAC registers determines
the analog output from the respective DACs. The WR input is
an edge-triggered input, and data is transferred into the selected
DAC register on the rising edge of WR. Holding CS and WR
low does not make the selected DAC register transparent. The
A/B input should not be changed while CS and WR are low.
CS
H
L
g
L
g
X
L = Low State, H = High State, X = Don’t Care
REV. B
Figure 8. AD7569/AD7669 Write Cycle Timing Diagram
WR
H
g
L
g
L
X
Figure 7. AD7569 DAC Input Control Logic
A/B
X
L
L
H
H
X
Table III. AD7669 DAC Truth Table
RESET
H
H
H
H
H
L
DAC Function
DAC Registers Unaffected
DACA Register Updated
DACA Register Updated
DACB Register Updated
DACB Register Updated
DAC Registers Loaded with
All Zeros
–11–
The contents of the DAC registers are reset to all 0s by an active
low pulse on the RESET line, and for the unipolar output
ranges, the outputs remain at 0 V after RESET returns high.
For the bipolar output ranges, a low pulse on RESET causes the
outputs to go to negative full scale. In unipolar applications, the
RESET line can be used to ensure power-up to 0 V on the
AD7669 DAC outputs and is also useful when used as a zero
override in system calibration cycles. If the RESET input is con-
nected to the system RESET line, then the DAC outputs reset
to 0 V when the entire system is reset. Figure 9 shows the DAC
input control logic for the AD7669, and the write cycle timing
diagram is shown in Figure 8.
ADC Timing and Control
The ADC on the AD7569/AD7669 is capable of two basic oper-
ating modes. In the first mode, the ST line is used to start con-
version and drive the track-and-hold into hold mode. At the end
of conversion, the track-and-hold returns to its tracking mode.
The second mode is achieved by hard-wiring the ST line high.
In this case, CS and RD start conversion, and the microproces-
sor is driven into a WAIT state for the duration of conversion by
BUSY.
Figure 10. ADC Mode 1 Interface Timing
Figure 9. AD7669 DAC Control Logic
AD7569/AD7669