AD7869JN Analog Devices Inc, AD7869JN Datasheet - Page 4

• Manufacturer Part Number: AD7869JN
• Description: IC I/O PORT 14BIT ANLG 24-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7869JN

• Rohs Status: RoHS non-compliant
• Applications: Analog I/O
• Interface: TTL/CMOS
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 24-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Converter Type: ADC/DAC
• Resolution: 14b
• Number Of Dac's: Single
• Data Rate: 0.083MSPS
• Digital Interface Type: Serial
• Pin Count: 24
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

AD7869
TIMING SPECIFICATIONS
Parameter
ADC TIMING
DAC TIMING
NOTES
1
2
3
4
5
6
ABSOLUTE MAXIMUM RATINGS*
(T
V
V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
V
V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7869 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Timing specifications are sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
Serial timing is measured with a 4.7 k
When using internal clock, RCLK mark/space ratio (measured form a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space
ratio = external clock mark/space ratio.
DR will drive higher capacitance loads but this will add to t
Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
TCLK mark/space ratio is 40/60 to 60/40.
DD
SS
OUT
IN
A
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
l2
13
= + 25 C unless otherwise noted)
3
4
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
to AGND . . . . . . . . . . . . . . . . V
5
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Limit at T
(All Versions)
50
440
100
20
100
155
4
100
2 RCLK + 200 to
3 RCLK + 200
50
75
150
30
75
40
Model
AD7869JN
AD7869JR
AD7869AQ
*N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
MIN
pull-up resistor on DR and RFS and a 2 k pull-up resistor on RCLK. The capacitance on all three outputs is 35 pF.
, T
1, 2
MAX
SS
–0.3 V to V
(V
–40 C to +85 C
Temperature
Range
0 C to +70 C
0 C to +70 C
DD
= +5 V
5
Units
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
since it increases the external RC time constant (4.7 k //C
DD
DD
DD
DD
DD
DD
DD
SS
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
5%, V
ORDERING GUIDE
to V
DD
SS
Signal-
to-Noise
Ratio (SNR)
78 dB
78 dB
77 dB
= –5 V
–4–
Operating Temperature Range
Storage Temperature Range . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300 C
Power Dissipation (Any Package) to +75 C . . . . . . . 1000 mW
Derates above +75 C by . . . . . . . . . . . . . . . . . . . . 10 mW/ C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
J Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
A Version . . . . . . . . . . . . . . . . . . . . . . . . . . –40 C to +85 C
5%, AGND = DGND = 0 V)
Conditions/Comments
CONVST Pulse Width
RCLK Cycle Time, Internal Clock
RFS to RCLK Falling Edge Setup Time
RCLK Rising Edge to RFS
RCLK to Valid Data Delay, C
Bus Relinquish Time after RCLK
CONVST to RFS Delay
TFS to TCLK Falling Edge
TCLK Falling Edge to TFS
TCLK Cycle Time
Data Valid to TCLK Setup Time
Data Valid to TCLK Hold Time
LDAC Pulse Width
Relative
Accuracy
2 LSB max
2 LSB max
2 LSB max
L
) and hence the time to reach 2.4 V.
Package
Option*
N-24
R-28
Q-24
WARNING!
L
= 35 pF
ESD SENSITIVE DEVICE
REV. A